JPS6126700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a memory series switching circuit capable of expanding a plurality of series of memories outside the basic part of a computer.

The area that a computer can directly read and write, that is, the address area, usually has 2 ⁿ addresses, where n is the number of address buses the computer has. For example, the currently most common 8-bit parallel processing microcomputer has 16 address buses, and thus has an address area of 2 ¹⁶ =65536 addresses. Then, a memory for holding data and an input/output port for exchanging data with external devices can be assigned to each address. However, with the rapid decline in memory prices in recent years, it has become economically possible to have a memory with a large memory capacity, which requires a large address area, and the number of cases where the address area is insufficient has increased. In such cases, a bank switching method is a commonly used method for expanding the address area.

The bank switching method will be explained below. 1st
The figure is a configuration diagram of a computer system using the bank switching method. In Fig. 1, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is a data holding circuit (hereinafter abbreviated as register), 3 is a decoder, 4 is a data bus, 6 is a first series memory, and 7 is a second series memory. 8 is a third series memory, 9 is a fourth series memory, 10 is a series selection signal, and 11 is a memory for an operating system (hereinafter abbreviated as OS).

In FIG. 1, when the CPU ₁ writes the sequence number that it wishes to access from now on to the register 2, the decoder 3 selects only one sequence memory among 6 to 9 that matches the sequence number and outputs the sequence selection signal 10.
becomes effective. The OS memory 11 generally records procedures for managing the basic operations of the entire system, including these switching controls.
It is accessible no matter which series is selected.

The bank switching method described above has the advantages of (1) increasing the total address area of the CPU, and (2) easy switching when processing multiple tasks in parallel, but it also has the following problems. be.

(1) It is necessary to prepare hardware for bank switching in the main body in advance.

(2) It is difficult to expand the number of sequences beyond the preset upper limit.

Therefore, computer systems that do not take into account expansion of the address area using bank switching in advance,
Alternatively, in systems where the number of sequences is insufficient due to insufficient consideration, it becomes difficult to further expand the memory, which poses a problem. The following methods have been considered to deal with this problem.

This method will be explained using FIG. 2. In Figure 2, 1 is the CPU, 4 is the address bus, 5 is the data bus, 11 is the OS memory, 12 is the register,
13 is a preset switch, 14 is a comparison circuit, 1
5 is a coincidence signal, 16 is a memory, and 17 is an expansion memory card. In FIG. 2, the aforementioned CPU ₁ , address, bus, data bus, and OS memory 11 are the same as those in FIG. 1. The register 12 has almost the same function as the register 2 in FIG. 1, but there is one for each series, and the CPU ₁ writes to all the registers 12 in parallel. The preset switch 13 is, for example,
This is a switch such as a DIP switch that sets its own sequence number in advance, and only when the data held in the register 12 and the data set in the preset switch 13 are equal by the comparison circuit 14, The coincidence signal 15 becomes active. Of all the series, only the memories 16 of the series in which the coincidence signal 15 is active are valid, and all the memories 16 of the other series are invalid. Therefore, expansion memory card 1 with the same series number and the same area
Except for case 7, it is possible to additionally connect as many expansion memory cards 17 as the drive capacity of the address bus and data bus allows. In addition, it is possible to have up to 256 sequence numbers, for example, only in the case of 8-bit parallel data, so you can decide on a fixed sequence number depending on the mode or type of work in advance, and select the sequence number you need at any given time. It is also possible to use a combination of several expansion memory cards 17. However, this method also has the following drawbacks. (1) In order for the CPU to know which memory card is selected among the memory cards 17, it is necessary to read the set value of the register held in the selected memory card, but this is difficult. In particular, if all registers 12 connected in parallel are attempted to be read simultaneously, data conflicts may occur due to differences in propagation delay times, potentially shortening the life of the IC. (2) In order to prevent program runaway, it is necessary to determine whether a desired sequence memory exists when selecting a memory, but this determination tends to be complicated.

These drawbacks have caused problems such as complication of software processing and restrictions on use.

It is an object of the present invention to provide a memory series that eliminates the drawbacks of the prior art described above, makes it possible to read the series number set in the selected register 12, and allows easy checking of the presence or absence of each series. To provide an expansion circuit.

In order to achieve the above purpose, the match signal is used to output the series number on the data bus only from the memory cards of the series for which the match signal is valid, and the CPU reads it to output the series number on the data bus. This allows you to identify memory cards under your control.

A specific embodiment according to the present invention will be described below with reference to FIG. FIG. 3 is a block diagram of an embodiment in which the present invention is applied to the expansion memory card 17 in FIG. 2. In FIG. 3, 18 is a buffer circuit, 19 is a pull-up resistor, 20 is a register write pulse, 21 is a register read pulse, and 2
2 is an AND circuit. 5, 12 in Figure 3
Each block numbered 16 to 16 is the same as the block with the same number in FIG. Further, an address bus and a data bus input/output to/from the memory 16 are omitted for convenience of explanation. The operation of this embodiment will be explained using FIG. The operating principle of sequence selection in this embodiment is as described in the explanation of FIG. The major difference from the conventional example is that the coincidence signal 15, which is the output signal of the comparison circuit 14 mentioned above, is not only inputted to the memory 16 as a valid/invalid control signal, but also inputted to the AND circuit 22. The AND circuit 22 ANDs the register read pulse 21 and outputs it as an output control signal for the buffer circuit 18.

As described above, the CPU ₁ writes the series number corresponding to the memory card selected by the CPU 1 to each register 12 of the memory card 17 in the write state, and selects the memory card ( In other words, only the matching signal of the memory card selected by the CPU is made active. Therefore, only the buffer 18 of the memory card selected by the CPU can be output. next
The CPU enters the read state and can identify the memory card it is currently managing by reading the series number output from the buffer 18 of the selected memory card onto the data bus 5.

Buffer 18 is high impedance, ie, disconnected from data bus 5, except when match signal 15 is active. The pull-up resistor 19 is provided to provide all bits of data at "H" level whenever the data bus 5 is in a high impedance state. By doing this, even if multiple expansion memory cards 17 are inserted, the data held in the register 12 written in parallel by the CPU ₁ and the data in the preset switch 13 will match, that is, the currently selected sequence. Only the registers 12 of the series are read. As a result, in addition to avoiding conflicts on the data bus, if there is no sequence that matches the sequence number written in the register 12, when the register 12 is read, there is no corresponding register 12, so the buffer 18 at that time is
The output is in a high impedance state, and due to the action of the pull-up resistor 19, all bits of data are at the "H" level, regardless of the setting value of the register 12. Therefore, all bits are “H”
If you make a promise that if it is level, that is, 8-bit parallel data, there will be no hexadecimal (FF) series, you can easily check whether the specified series exists.

Therefore, it is possible to prevent harmful effects such as data destruction due to writing to the wrong memory series and data being erased due to writing to a non-existent memory series.

By implementing the present invention, it becomes possible to directly read the register holding the currently selected series number without causing a data conflict, and it becomes possible to directly read the register holding the currently selected series number without causing a data conflict. Processing on the hardware can be accelerated and simplified. Furthermore, it is extremely easy to know whether each series exists or not.

Therefore, accessing the wrong memory card may cause the CPU to read or write incorrect data or programs, causing the device to run out of control.
Data loss can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a first conventional example, FIG. 2 is a block diagram for explaining a second conventional example, and FIG. 3 is a block diagram showing an embodiment according to the present invention. . 12...Register, 13...Preset switch,
14... Comparison circuit, 15... Matching circuit, 18... Buffer circuit, 19... Pull-up resistor, 22... AND circuit.

Claims (1)

[Claims] 1. A data holding circuit that can be attached to a digital signal processing device having a bus line type central processing unit and that can set arbitrary data from the central processing unit, and a data holding circuit that can be set with fixed data or arbitrary data in advance. A setting means, a data comparison means that outputs a valid signal only when the set data values of both the setting means and the data holding circuit correspond, a memory whose validity can be controlled by the valid signal, and the valid signal, A memory series expansion circuit comprising means for controlling reading of data held by the data holding circuit.