JPS61276264A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the peeling of a metallic silicide film, and to increase the withstand voltage of an inter-layer insulating film as an upper layer by a method wherein a gate electrode is formed, a first insulating film except a section under the gate electrode is removed, source-drain regions are shaped, a second insulating film is deposited and formed onto the whole surface and the whole is thermally treated. CONSTITUTION:A field insulating film 12, a gate insulating film 13, a polycrystalline silicon film 14 and a high melting-point metallic silicide film 15 are formed onto the main surface of a substrate 11. A gate electrode 17 is shaped by using a resist film 16 as a mask. The gate electrode 17 is shaped by using a resist film 16 as a mask. The gate insulating film 13 in sections except a section under the gate electrode 17 is removed through a wet etching method. The ions of another conduction type impurity such as arsenic are implanted by employing the field insulating film 12 and the gate electrode 17 as masks to shape N-type source-drain regions 18 in the silicon substrate 11. An silicon dioxide film 19 as a second insulating film is deposited in comparatively large thickness, and the silicon dioxide film 19 is solidified through heat treatment, while the source-drain regions 18 are activated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a semiconductor device having an MO8 field effect transistor whose reliability is improved by improving the interlayer insulating film. Relating to a manufacturing method.

[Conventional technology]

As a method for manufacturing a semiconductor device having an MOa field effect transistor, the method shown in FIG. 2 4-(q) has conventionally been used.

That is, as shown in FIG. 5 (5), a field insulating film 2 made of silicon dioxide is formed on the main surface of a silicon substrate 1 of negative conductivity type using a selective oxidation method, and then silicon dioxide is formed using a thermal oxidation method. A gate insulating film 3 made of silicon is formed. Then, a polycrystalline silicon (polysilicon) film 4 doped with impurities such as phosphorus and a high melting point metal silicide film 5 (for example, a tungsten silicide (WSi film)) are deposited in a laminated state, and then a photoresist 6 is used as a mask. A pattern is formed into a predetermined shape to form a gate electrode 7.

Next, in order to repair the gate insulating film 3t that was damaged during the process of forming the gate electrode 7, as shown in FIG. A thin oxide film 9 is then formed again. Then, using the gate electrode 7 and the field insulating film 2 as a mask, another high-concentration quaternary type impurity layer 8 is formed as a source/drain region by thermal diffusion or ion implantation.

Thereafter, as shown in FIG. 0, a phosphosilicate glass (PSG) film 10 is formed on the entire surface to form an MO8 type field effect transistor element.

[Problem that the invention seeks to solve]

In the MO8 type field effect transistor having the above-described configuration, the gate electrode 7 is formed of the thin polysilicon group 4 and the low-resistance tungsten silinide film 5, so that the gate electrode 7 can be made thinner and its pattern accuracy can be improved. This is effective for increasing the density and integration of semiconductor devices.

However, in manufacturing it, the entire process of removing the -H gate insulating film 3 after forming the gate electrode 7 and forming a thin oxide film 9 in a thermal oxidation atmosphere is necessary.
Because the impurity diffusion coefficient in the tungsten silicide film 5 is extremely large, the impurity (phosphorus) in the polysilicon film 4 is diffused into the substrate via the tungsten silicide film 5, making the characteristics of the transistor unstable. There is a problem of becoming. Further, this thermal oxidation treatment causes a problem in that the tungsten silicide film 5 is likely to peel off.

-1. In the above manufacturing method, in order to prevent a steep step in the southern part of the gate electrode 7 of the PSG film 10,
The film 10 is heat-treated to give it fluidity and then deposited on the thin oxide film 9 to alleviate the step difference, but this treatment makes the PSG film 10 at the end of the Sigut electrode 7 thinner. C, PSG film lO as an interlayer insulating film in this part
Problems have also arisen in that the pressure resistance of the metal is reduced.

[Means for solving problems]

In the method for manufacturing a semiconductor device of the present invention, in order to prevent peeling at the gate electrode and improve the withstand voltage of the interlayer insulating film, the first step is performed during the manufacturing process of the MO8 type field effect transistor.
forming a gate electrode made of polycrystalline silicon and a silicide film on the insulating film, and then removing the first insulating film except under the gate electrode and forming source/drain regions on predetermined portions of the semiconductor substrate. The second insulating film is deposited on the entire surface including the gate electrode and source/drain regions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 4-4(g) are process sectional views for explaining one embodiment of the present invention.

First, as shown in FIG.
A thick silicon dioxide film is formed in a required region on the main surface of the field insulation film 12 by a known selective oxidation method to form a field insulation film 12t, and a first insulation film is formed in the region defined by the field insulation film 12. A gate insulating film 13 made of a thin silicon dioxide film has a corrugated shape. CV on top of that
A thin polycrystalline silicon film 14 is formed by the D method, and phosphorus is introduced into it to reduce its resistance. Furthermore, a high melting point metal silicide film (tungsten silicide film: WSiz in this example) 15 is formed thereon by CVD or sputtering. Then, using the photoresist film 16 formed in a desired pattern as a mask, the polycrystalline silicon film 14 and the tungsten silicide film 15 are dry-etched to form a gate electrode 17 with a two-layer structure called polycide, as shown in FIG. Form.

Next, as shown in FIG. 3(q), the gate insulation layer of the portion other than the bottom of the gate electrode 17, which was damaged in the process of forming the gate electrode 17, is removed by wet etching. Then, in this state, the field Using the insulator P12 and the gate electrode 17 as a mask, another 4-type impurity such as arsenic is ion-implanted to form an N-type source/drain region 18 in the silicon substrate 11.

Then, as shown in the same figure (b), the second
A silicon dioxide film 19 as an insulating film is deposited relatively thickly, and then heat treatment is performed in an atmosphere of 9 elements to harden the silicon dioxide film 19 and to activate the source/drain regions 18.

At this time, the main surface of the silicon substrate 1 or the gate electrode 17
A thin thermally oxidized silicon film 21 is formed on the surface.

Thereafter, after forming the PSG film 20 on the entire surface as in the same case (2), the P8G film 20iC is heat-treated in an oxidizing atmosphere to impart fluidity in order to alleviate the step difference at the end of the gate electrode 17. Thereafter, an opening is opened through this PSG@l, the CVD dioxide silicon dioxide film 19 and the thermal oxidation silicon film 21t, and the aluminum wiring is opened. 22 and connection with the source/drain regions 18, a 9N channel MO8 type field effect transistor is completed.

Therefore, according to the MO8 type field effect transistor formed in this way, the gate 1! After removing the gate insulating film 13t except under the electrode 17, a silicon dioxide film 19 is formed by the CVI) method, and then the source film 13t is removed.
Since ion implantation and heat treatment are performed on the drain region 18, it is possible to prevent impurities from diffusing into the silicon substrate 11 from the polycrystalline silicon film 11) of the gate electrode 17, preventing contamination of the silicon substrate 11 and stabilizing the transistor. It is possible to aim for Furthermore, since the gate electrode 17 is covered with the CVD silicon dioxide film 19 during this heat treatment, the tungsten silicide film 15 is not peeled off.

10,000, since there is a relatively thick CVD silicon dioxide a19 on the gate electrode 17, the upper layer of PEG
When fluidity is imparted to the film 20, even when the thickness of the PSG film 2 at the end of the gate electrode 17 is reduced to 0, the withstand voltage of the interlayer insulating film as a whole can be improved and reliability can be improved.

Note that in the above embodiment, the N
Although an example of manufacturing a channel MO8 type field effect transistor has been described, it can be similarly applied to manufacturing a P channel MO8 type field effect transistor in which a P type source/drain region is formed on an N type silicon substrate, or an example of manufacturing a 0 MO8 type field effect transistor.
It can also be applied to device manufacturing. In addition to the above-mentioned tungsten, molybdenum (MO) and other metals can also be used as the metal silicide film forming the gate electrode.

〔Effect of the invention〕

As explained above, the present invention provides a method for removing the first insulating film except under the gate electrode after forming the gate electrode.
A drain region is formed, and then a second isolation region is formed on the entire surface.
Since the film is deposited and heat treated, it is possible to prevent impurities from the two-layered gate electrode from diffusing into the substrate and making the transistor unstable, and also to prevent the metal silicide film from peeling off. Furthermore, the withstand voltage of the upper interlayer insulating film can be improved, which has the effect of making it possible to manufacture highly reliable semiconductor devices.

[Brief explanation of drawings]

Figures 1 (5) to (2) are cross-sectional views for explaining an embodiment of the present invention in the order of the manufacturing process, and Figures 2 (5) to (q are cross-sectional views for explaining the conventional method). 1.11... Silicon substrate, 2.12... Field insulating film, 3.13... Gate insulating film (first insulating film), 4.14... Polycrystalline silicon m, 5. 15...
Tungsten silicide! , 6.16... Photoresist, 7#17... Gate electrode, 8.18... Source/drain region, 9.19... Silicon dioxide film (
second insulating film), 10.20...PSG film, 21...
・Silicon dioxide film. Agent Patent attorney Susumu Uchihara - Pregnancy 1 figure

Claims (1)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate and forming a gate electrode made of a polycrystalline silicon film and a metal silicide film thereon;
a step of removing the insulating film of the semiconductor substrate, a step of forming source/drain regions at predetermined portions of the semiconductor substrate, and a step of forming a second insulating film on the entire surface.
1. A method of manufacturing a semiconductor device, the method comprising: forming an insulating film. 2. The method of manufacturing a semiconductor device according to claim 2, wherein a predetermined heat treatment is performed after forming the second insulating film.