JPS61280672A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS61280672A JPS61280672A JP10777085A JP10777085A JPS61280672A JP S61280672 A JPS61280672 A JP S61280672A JP 10777085 A JP10777085 A JP 10777085A JP 10777085 A JP10777085 A JP 10777085A JP S61280672 A JPS61280672 A JP S61280672A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- photoresist film
- gate
- electrode material
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000007772 electrode material Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001704 evaporation Methods 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 239000010936 titanium Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 3
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 101001002470 Homo sapiens Interferon lambda-1 Proteins 0.000 description 1
- 102100020990 Interferon lambda-1 Human genes 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ） 産業上の利用分野
本発明は化合物半導体装置、特にＧａＡｓ−ＦＥＴの製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a compound semiconductor device, particularly a GaAs-FET.
（ロ）従来の技術
ＧａＡｓ−ＦＥＴやＧａＡｓ−ＩＣの性能を向上するＫ
は極めて短かいゲート長のゲート電極の形成を必要とし
、サブミクロン領域の加工技術が必要となる。(b) K that improves the performance of conventional technology GaAs-FET and GaAs-IC
This requires the formation of a gate electrode with an extremely short gate length, which requires processing technology in the submicron region.
第２図にＧａＡｓ −Ｆ Ｅ Ｔの断面図を示す。Ｇａ
Ａｓ基板結晶Ｃ！υの表面に離間してソース電極口およ
びドレイン’１ｔｓ（ハ）を設け、この間妊ゲート電極
（財）を設けている。半絶縁性のＧａＡｓ基板Ｃ！υ内
にオーミックコンタクトをとるためのＮ＃（至）とＦＥ
Ｔ動作をさせる能動層□□□の領域がある。性能向上の
ためにはゲート電極Ｑ４Ｊの巾を短かくして静電容量を
小さくする必要がある。斯るＧａＡｓ−ＦＥＴの先行技
術としては例えば特開昭５９−２３５６５号公報（ＨＯ
ＩＬ２９／８０）がある。FIG. 2 shows a cross-sectional view of GaAs-FET. Ga
As substrate crystal C! A source electrode opening and a drain '1ts (c) are provided spaced apart on the surface of υ, and a gate electrode (c) is provided between them. Semi-insulating GaAs substrate C! N# (to) and FE to make ohmic contact within υ
There is a region of the active layer □□□ that causes T operation. In order to improve performance, it is necessary to reduce the capacitance by shortening the width of the gate electrode Q4J. As a prior art of such GaAs-FET, for example, Japanese Patent Application Laid-Open No. 59-23565 (HO
IL29/80).
斯るＧａＡｓ−ＦＥＴではゲート電極（２勾を第３図に
示す如くり７トオフ法で形成している。即ち第３図イに
示す如く、ＧａＡｓ基板（２１Ｉ上にソース電極■およ
びドレイン電極［有］を形成した後予定のゲート領域と
なる部分忙開孔＠を有するホトレジスト１曽で被覆する
。このホトレジスト層（至）の開孔＠はゲート電極Ｉ２
４のゲート巾を決定している。次に第３図口に示す如く
、ゲート電極（ロ）の電極材料を蒸着する。電極材料と
してはアルミニウムを用いる。その後第３図へに示す如
（、ホトレジスト層（ハ）をエツチング除去するり７ト
オ７法により所望のゲート電極（財）を形成している。In such a GaAs-FET, the gate electrode (2 slopes) is formed by the 7-off method as shown in FIG. 3. That is, as shown in FIG. After forming the gate electrode I2, the photoresist layer 1 is coated with a photoresist layer having a partial opening which will become the intended gate region.
The gate width of 4 has been determined. Next, as shown in the opening of FIG. 3, electrode material for the gate electrode (b) is deposited. Aluminum is used as the electrode material. Thereafter, as shown in FIG. 3, the photoresist layer (c) is removed by etching, and a desired gate electrode is formed by the 7-to-7 method.
（ハ）発明が解決しようとする問題点
しかしながら斯上したＧａＡｓ−ＦＥＴではゲート電極
（２）と対応するようく前記ホトレジスト膜（至）を開
孔するため、このホトレジスト膜（至）の開孔（２）が
ゲート電極−のゲート幅を決定する。従つ℃前記ゲート
幅には限界があった。(c) Problems to be solved by the invention However, in the above-mentioned GaAs-FET, since the photoresist film (to) is opened to correspond to the gate electrode (2), the opening in this photoresist film (to) is difficult. (2) determines the gate width of the gate electrode. Therefore, there is a limit to the gate width.
に）問題点を解決するだめの手段
本発明は断点に鑑みてなされ、前記ゲート領域（９）お
よびホトレジスト膜（６）上にゲート電極材料（８）を
斜め蒸着することで従来の欠点を大幅に改善した化合物
半導体装置の製造方法を実現するものである。B) Means for Solving the Problems The present invention has been made in view of the drawbacks, and obliquely deposits the gate electrode material (8) on the gate region (9) and the photoresist film (6), thereby solving the conventional drawbacks. This realizes a significantly improved method of manufacturing compound semiconductor devices.
（ホ）作用
本発明に依ればゲート電極材料（８）を斜め蒸着するの
で蒸着角度とＧａＡｓ基板（１７表面からホトレジスト
膜（６）までの厚さおよび開孔（７）の大きさでＧａＡ
ｓ基板（１）に形成されるゲート電極（９）のゲート幅
を決定できる。従って蒸着角度を大。きくし、セしてＧ
ａＡｓ基板（１７表面からホトレジスト膜（６）までの
厚さを厚くし更に開孔（８）を狭くすることでゲート幅
を小さく形成できる。(E) Function According to the present invention, since the gate electrode material (8) is deposited obliquely, the deposition angle, the thickness from the surface of the GaAs substrate (17) to the photoresist film (6), and the size of the opening (7)
The gate width of the gate electrode (9) formed on the s-substrate (1) can be determined. Therefore, increase the deposition angle. Listen, set and G
The gate width can be made small by increasing the thickness from the surface of the aAs substrate (17) to the photoresist film (6) and narrowing the opening (8).
（へ）実施例
以下に本発明の実施例を第１図イ乃至第１図トを参照し
ながら詳述する。(F) Embodiments Below, embodiments of the present invention will be described in detail with reference to FIGS. 1A to 1G.
本発明の第１の工程は、ＧａＡｓ基板（１）上に離間し
てソースおよびドレイン電極（２７＋３３を形成するこ
とＫある。（第１図イ乃至第１図二参照）。The first step of the present invention is to form source and drain electrodes (27+33) spaced apart on a GaAs substrate (1) (see FIGS. 1A to 1B).
ＧａＡｓ基板（１）は半絶縁層とその上ＫＮ型のバッフ
ァ層とＮｆｆ１の動作層とをダブルエピタキシャル成長
して形成されている。基板（１７表面には第１図イに示
す如く、絶縁膜であるシリコン酸化膜（４）を全面にＣ
ＶＤ法等で付着し、予定のソースおよびドレイン電極（
２１＋３１部分を除いて絶縁膜（４）上をホトレジスト
層（５）で被覆する。続いてこのホトレジスト層（５）
をマスクとして絶縁膜（４）をエツチングし、予定のソ
ースおよびドレイン電極（２１（３）部分を形成する部
分の基板（１）を露出する。その後金面に金−ゲルマニ
ウム（Ａｕ−Ｇｅ）を蒸着して第１図口に示す如く、基
板（１）上にソースおよびドレイン電極＋２１ （３１
を付着する。更にホトレジスト層（５）をエツチングす
るリフトオフ法によりホトレジスト層（５）上の金−ゲ
ルマニウムを除去して第１図ノ１に示す如く、ソースお
よびドレイン電極（２Ｈ３１を形成している。The GaAs substrate (1) is formed by double epitaxially growing a semi-insulating layer, a KN type buffer layer and an Nff1 active layer thereon. A silicon oxide film (4) as an insulating film is coated on the entire surface of the substrate (17, as shown in Figure 1A).
It is attached by VD method etc. and the planned source and drain electrodes (
The insulating film (4) is covered with a photoresist layer (5) except for the 21+31 portion. Next, this photoresist layer (5)
Using this as a mask, the insulating film (4) is etched to expose the portion of the substrate (1) that will form the source and drain electrodes (21 (3)). Thereafter, gold-germanium (Au-Ge) is etched on the gold surface. By vapor deposition, source and drain electrodes +21 (31
Attach. Further, the gold-germanium on the photoresist layer (5) is removed by a lift-off method of etching the photoresist layer (5) to form source and drain electrodes (2H31) as shown in FIG.
本工程でソースおよびドレイン電極（２１＋３１間の基
板（１）表面は絶縁膜（４）で被覆される。その後前記
絶縁膜（４）およびソースおよびドレイン電極（２１（
３１上を第１図二の如くホトレジスト膜（６）で被覆す
る。In this step, the surface of the substrate (1) between the source and drain electrodes (21+31) is covered with an insulating film (4). Then, the insulating film (4) and the source and drain electrodes (21 (
31 is covered with a photoresist film (6) as shown in FIG.
本発明の第２の工程は前記ゲート電極（９）と対応する
ように前記ホトレジスト膜（６）を開孔し、前記ホトレ
ジスト膜（６）をマスクとして前記絶縁膜（４）を蝕刻
することにある（第１図ホ参照）。The second step of the present invention is to open a hole in the photoresist film (6) so as to correspond to the gate electrode (9), and to etch the insulating film (4) using the photoresist film (6) as a mask. Yes (see Figure 1 E).
本工程では前記ホトレジスト層（６）にゲート電極（９
）のゲート長より大きい開孔（７）を設ける。これは次
の工程で斜めに蒸着をするためゲート電極（９）は目的
とするゲート長より大きい必要がある。In this step, the gate electrode (9) is attached to the photoresist layer (6).
) is provided with an aperture (7) larger than the gate length. This is because the gate electrode (9) needs to be larger than the intended gate length because it will be deposited obliquely in the next step.
本発明の第３の工程は前記ゲート領域（９）およびホト
レジスト膜（６）上にゲート電極材料（８）例えばチタ
ン、白金、金等を斜め蒸着することにある。The third step of the invention consists in obliquely depositing a gate electrode material (8) such as titanium, platinum, gold, etc. on the gate region (9) and the photoresist film (6).
（第１図へ参照）
本工程は本発明の特徴とするところであり蒸着角度とＧ
ａＡｓ基板（１）表面からホトレジストＨ（６）までの
厚さ、更には開孔（７）の大きさを制御することでＧａ
Ａｓ基板（１）Ｋ形成されるゲート電極（９）のゲート
幅を決定できる。理論的には絶縁膜（４）の厚さを１μ
ｍ、ホトレジスト膜（６）の厚さを０．５μｍ、開孔（
８）の大きさを１μｍとし、基板（１１の垂直方向より
約１８° 傾けることでゲート幅は０．５μｍとなる。(Refer to Figure 1) This process is a feature of the present invention, and is characterized by the deposition angle and G
By controlling the thickness from the aAs substrate (1) surface to the photoresist H (6) and the size of the opening (7), Ga
The gate width of the gate electrode (9) formed on the As substrate (1) can be determined. Theoretically, the thickness of the insulating film (4) should be 1μ.
m, the thickness of the photoresist film (6) is 0.5 μm, the opening (
8) is 1 μm in size, and the gate width is 0.5 μm by tilting the substrate (11) by about 18° from the vertical direction.
従って前記蒸着角度とＧａＡｓ基板（１）表面からホト
レジスト膜（６）までの厚さおよび開孔（８）の大きさ
でゲート幅を制御できる。Therefore, the gate width can be controlled by the evaporation angle, the thickness from the surface of the GaAs substrate (1) to the photoresist film (6), and the size of the opening (8).
本発明の第４の工程は前記ゲート電極材料（８）をＩＪ
７トオフしてゲート電極（９）を形成することにある。The fourth step of the present invention is to apply the gate electrode material (8) to IJ.
7 to form a gate electrode (9).
本工程ではホトレジスト層（６）をエツチング除去する
リフトオフ法により所望のゲート電極（９）を残して他
の電極材料（８）を除去する。In this step, a desired gate electrode (9) is left and other electrode materials (8) are removed by a lift-off method in which the photoresist layer (6) is etched away.
（ト）発明の効果
本発明に依ればゲート電極材料（８）の蒸着角度とＧａ
Ａｓ基板（１１表面からホトレジスト膜（６）までの厚
さ、更には開孔（８）の大きさを制御することでＧａＡ
ｓ基板（１）く形成されるゲート電極（９）のゲート幅
を決定できたため静電容量を小さくでき性能を向上させ
ることができる。(g) Effect of the invention According to the invention, the vapor deposition angle of the gate electrode material (8) and the Ga
By controlling the thickness from the surface of the As substrate (11) to the photoresist film (6) and the size of the openings (8), GaA
Since the gate width of the gate electrode (9) formed on the s-substrate (1) can be determined, the capacitance can be reduced and the performance can be improved.
第１図イ乃至第１図トは本発明の化合物半導体装置の製
造方法を説明する断面図、第２図は従来のＧａＡｓ −
Ｆ Ｅ Ｔの構造を説明する断面図、第３図イ乃至第３
図ハは従来のＧａＡｓ−ＦＥＴの製造方法を説明する断
面図である。
主な図番の説明
＋１．１はＧａＡｓ基板、＋２１Ｆ３１はソースおよび
ドレイン電極、（４）は絶縁膜、（５１（６１はホトレ
ジスト膜、（７）は開孔、（８）はゲート電極材料、（
９）はゲート電極である。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 静 失
策１図二
第１図ホ
＠１図へ
第１図ト
第２図
第３図イ
第３図口
第３図ハ1A to 1G are cross-sectional views for explaining the method of manufacturing a compound semiconductor device of the present invention, and FIG. 2 is a cross-sectional view of a conventional GaAs-
Cross-sectional views explaining the structure of FET, Figures 3A to 3
Figure C is a cross-sectional view illustrating a conventional method for manufacturing a GaAs-FET. Explanation of main figure numbers +1.1 is GaAs substrate, +21F31 is source and drain electrode, (4) is insulating film, (51 (61 is photoresist film, (7) is opening, (8) is gate electrode material, (
9) is a gate electrode. Applicant Sanyo Electric Co., Ltd. and 1 other representative Patent attorney Shizuka Sano Mistake 1 Figure 2 Figure 1 E @ Figure 1 Figure 1 To Figure 2 Figure 3 A Figure 3 mouth Figure 3 C
Claims (1)
ン電極を形成した後微小ゲート長のゲート電極を形成す
る化合物半導体装置の製造方法に於いて、 前記ソースおよびドレイン電極間の前記基板表面に形成
される絶縁膜およびソースドレイン電極上をホトレジス
ト膜で被覆する工程と、 前記ゲート電極と対応するように前記ホトレジスト膜を
開孔し、前記ホトレジスト膜をマスクとして前記絶縁膜
を蝕刻する工程と、 前記ゲート領域およびホトレジスト膜上にゲート電極材
料を斜め蒸着する工程と、 前記ゲート電極材料をリフトオフしてゲート電極を形成
する工程とを具備することを特徴とする化合物半導体装
置の製造方法。(1) In a method for manufacturing a compound semiconductor device in which a gate electrode with a minute gate length is formed after forming source and drain electrodes on a predetermined compound semiconductor substrate, forming a hole in the photoresist film to correspond to the gate electrode and etching the insulating film using the photoresist film as a mask; 1. A method for manufacturing a compound semiconductor device, comprising: diagonally depositing a gate electrode material on a region and a photoresist film; and lifting off the gate electrode material to form a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10777085A JPS61280672A (en) | 1985-05-20 | 1985-05-20 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10777085A JPS61280672A (en) | 1985-05-20 | 1985-05-20 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61280672A true JPS61280672A (en) | 1986-12-11 |
Family
ID=14467567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10777085A Pending JPS61280672A (en) | 1985-05-20 | 1985-05-20 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61280672A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5543888A (en) * | 1978-09-22 | 1980-03-27 | Nec Corp | Manufacture of junction gate type field effect transistor |
| JPS5673474A (en) * | 1979-11-20 | 1981-06-18 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
-
1985
- 1985-05-20 JP JP10777085A patent/JPS61280672A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5543888A (en) * | 1978-09-22 | 1980-03-27 | Nec Corp | Manufacture of junction gate type field effect transistor |
| JPS5673474A (en) * | 1979-11-20 | 1981-06-18 | Sumitomo Electric Ind Ltd | Manufacture of semiconductor device |
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