JPS61281561A - Manufacture of semiconductor-surface light-emitting element - Google Patents
Manufacture of semiconductor-surface light-emitting elementInfo
- Publication number
- JPS61281561A JPS61281561A JP60123072A JP12307285A JPS61281561A JP S61281561 A JPS61281561 A JP S61281561A JP 60123072 A JP60123072 A JP 60123072A JP 12307285 A JP12307285 A JP 12307285A JP S61281561 A JPS61281561 A JP S61281561A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- algaas
- substrate
- type
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000012010 growth Effects 0.000 claims abstract description 28
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 21
- 239000007791 liquid phase Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims description 22
- 238000005253 cladding Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 27
- 238000005530 etching Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- ZINJLDJMHCUBIP-UHFFFAOYSA-N ethametsulfuron-methyl Chemical compound CCOC1=NC(NC)=NC(NC(=O)NS(=O)(=O)C=2C(=CC=CC=2)C(=O)OC)=N1 ZINJLDJMHCUBIP-UHFFFAOYSA-N 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分町
この発明は光通信又は情報処理用の半導体面発光素子の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Applications) This invention relates to a method of manufacturing a semiconductor surface emitting device for optical communication or information processing.
(従来の技術)
この種の半導体面発光素子の一例が特願昭59−176
3号に提案されている。そこに提案された素子構造をA
I G a A s / G a A s系の発光ダ
イオードに適用した場合の、その製造方法は以下の通り
となる。(Prior art) An example of this type of semiconductor surface emitting device is disclosed in Japanese Patent Application No. 59-176.
It is proposed in No. 3. The device structure proposed there is A
When applied to an IGaAs/GaAs type light emitting diode, the manufacturing method thereof is as follows.
先ず、p型GaAs基板」二に電流狭窄のためのn型G
aAS電流ブロック層を一回目の液相エピタキシャル成
長(以下LPE成長と称する場合がある)させる。次に
、電流ブロック層に電流通路用の円形の穴をエツチング
形成し、次に、二回目のLPE成だを行ってp型A交G
aAsクラッド層、p型AJIGaAs活性層、n型A
JLG aA sクラッド層及びn型GaAsキャップ
層を連続して形成する。ここで、連続してとは二回目の
LPE成長工程の途中において、成長炉に対し、ウェハ
の出し入れを行わないことを意味する。First, a p-type GaAs substrate, and second, an n-type GaAs substrate for current confinement.
The aAS current blocking layer is grown by liquid phase epitaxial growth (hereinafter sometimes referred to as LPE growth) for the first time. Next, a circular hole for a current path is etched in the current blocking layer, and then a second LPE formation is performed to form a p-type AC
aAs cladding layer, p-type AJIGaAs active layer, n-type A
A JLG aAs cladding layer and an n-type GaAs cap layer are successively formed. Here, "continuously" means that wafers are not taken in and out of the growth furnace during the second LPE growth process.
(発明が解決しようとする問題点) 。(Problem that the invention seeks to solve).
上述した構造の素子を発光ピークが870nm以下の発
光素子に応用すると、活性層で発光した光の全パワーの
約50%がGaAs基板に吸収されてしまうという問題
がある。When the device having the above structure is applied to a light emitting device with an emission peak of 870 nm or less, there is a problem that about 50% of the total power of light emitted from the active layer is absorbed by the GaAs substrate.
この吸収を少なくするためには、GaAs基板の代り活
性層よりもエネルキーキャンプの大きなAMG aA
s基板を使用する必要がある。しかしながら、AfLG
aAsの表面は酸化され易いため、通常のウエッI・エ
ツチングを用いて電流ブロック層に電流通路用の穴を形
成すると、AuGaAs基板が外気に接触し、その表面
に酸化層が形成されてしまう。In order to reduce this absorption, AMG aA, which has a larger energy camp than the active layer, should be used instead of the GaAs substrate.
It is necessary to use an S substrate. However, AfLG
Since the surface of aAs is easily oxidized, if a hole for a current path is formed in the current blocking layer using ordinary wet I etching, the AuGaAs substrate will come into contact with the outside air and an oxidized layer will be formed on the surface.
これがため、穴形成後のAJLGaAs基板」二への二
回目の液相エピタキシャル成長は極めて困難であるとい
う問題があった。Therefore, there was a problem in that the second liquid phase epitaxial growth on the AJLGaAs substrate 2 after the holes were formed was extremely difficult.
この発明の目的は、AlGaAs基板の表面に酸化層を
生じさせることなく電流ブロック層に電流通路用の穴を
開けることが出来ると共に、この穴開けに連続してダブ
ルへテロ接合を構成する各層を困難無く成長させること
が出来る半導体面発光素子の製造方法を提供することに
ある。It is an object of the present invention to make it possible to make holes for current passage in a current blocking layer without forming an oxide layer on the surface of an AlGaAs substrate, and to continuously form holes in each layer constituting a double heterojunction after making the holes. An object of the present invention is to provide a method for manufacturing a semiconductor surface emitting device that can be grown without difficulty.
(問題点を解決するための手段)
この目的の達成を図るため、この発明によれば、先ず電
流ブロック層として供する第二導電型のGaAs予備基
板−1−に、第一導電型のAlGaAs層を成長させる
。この場合、このAlGaAs層の成長を液相エピタキ
シャル成長はもとより、他の任意好適な方法で行うこと
が出来る。また、このAlGaAs層のエネルギーギャ
ップを活性層の発光波長に対応するエネルギーギャップ
よりも犬きく設定しておく。(Means for Solving the Problem) In order to achieve this object, according to the present invention, first, an AlGaAs layer of the first conductivity type is added to the GaAs preliminary substrate-1 of the second conductivity type serving as a current blocking layer. grow. In this case, the AlGaAs layer can be grown not only by liquid phase epitaxial growth but also by any other suitable method. Further, the energy gap of this AlGaAs layer is set to be larger than the energy gap corresponding to the emission wavelength of the active layer.
次に、GaAs予備基板に厚みの中途までエツチングを
行って円形の溝を形成し、次にウェハを成長炉に入れ、
液相エピタキシャル成長時のメルトバックを用いて、G
aAs予備基板に、下地のAJIGaAs層に達する電
流通路用の穴を、形成する。この電流通路用の穴を形成
して残存した予備基板部分が電流ブロック層として作用
する。Next, the GaAs preliminary substrate is etched halfway through its thickness to form a circular groove, and then the wafer is placed in a growth furnace.
Using meltback during liquid phase epitaxial growth, G
A hole for a current path reaching the underlying AJI GaAs layer is formed in the aAs preliminary substrate. The spare substrate portion remaining after forming the hole for the current path acts as a current blocking layer.
このようにして形成されたGaAs電流ブロック層の下
地のAuGaAs層をこの面発光素子の本来の基板にす
る。尚、以下の説明においてこのAlGaAs層をAl
GaAs基板と称する場合がある。The AuGaAs layer underlying the GaAs current blocking layer thus formed is used as the original substrate of this surface emitting device. In the following explanation, this AlGaAs layer will be referred to as Al
Sometimes referred to as a GaAs substrate.
続いて、このウェハを成長炉外に取り出さずに、このよ
うな電流通路用の穴が形成されたウェハ上に、メルトバ
ック工程に引き続き、ダブルへテロ接合を形成するAl
GaAs第一クラ・ンド層、AJIGaAs活性層及び
AJLGaAs第二クラッド層をり次に液相エピタキシ
ャル成長させる。Next, without taking the wafer out of the growth reactor, Al was applied to form a double heterojunction following the meltback process on the wafer in which the holes for current paths were formed.
A first GaAs cladding layer, an AJI GaAs active layer, and a second AJLGaAs cladding layer are then grown by liquid phase epitaxial growth.
続いて、第二クラッド層上に直接、或いは所要に応じて
キャップ層等の層を液相エピタキシャル成長させた後、
蒸着或いはスパッタリング等の通常の半導体技術を用い
てn側及びp側電極をそれぞれ形成し、半導体面発光素
子を完成する。Subsequently, after growing a layer such as a cap layer directly on the second cladding layer or by liquid phase epitaxial growth as required,
The n-side and p-side electrodes are respectively formed using a normal semiconductor technique such as vapor deposition or sputtering to complete a semiconductor surface emitting device.
(作用)
このように、この発明によれば、同一の液相エタキシャ
ル成長工程中において、GaAs予備基板に対する電流
通路用の穴開けのためのメルトバックと、このメルトバ
ック工程に続くダブルヘテロ接合を構成する各層の成長
とを行うので、この液相エピタキシャル成長工程中に基
板となるべきAlGaAs基が外気に露出されることが
ない。従って、このAJIGaAs層の表面に酸化層を
生じさせることが無い。従って、ダブルへテロ接合層の
LPE成長を困難なく行える。(Function) As described above, according to the present invention, during the same liquid phase epitaxial growth process, meltback for forming a hole for a current path in a GaAs preliminary substrate and a double heterojunction following this meltback process are performed. Since each of the constituent layers is grown, the AlGaAs group that is to become the substrate is not exposed to the outside air during this liquid phase epitaxial growth process. Therefore, no oxide layer is formed on the surface of this AJI GaAs layer. Therefore, LPE growth of a double heterojunction layer can be performed without difficulty.
さらに、素子のAJLGaAs基板は光を吸収しないの
で、GaAs層を基板とする従来の場合よりも発光出力
が約二倍程度となる。Furthermore, since the AJLGaAs substrate of the device does not absorb light, the light emitting output is about twice that of a conventional case using a GaAs layer as a substrate.
(実施例)
以下、図面を参照して、この発明の半導体面発光素子の
実施例につき説明する。(Example) Examples of the semiconductor surface emitting device of the present invention will be described below with reference to the drawings.
第1図(A)〜(H)に示す製造工程図を参照して説明
する。尚、各図は主要製造段階でのウニ/\の状態を示
す断面図であり、断面を表わす/\ラッチングは一部分
を除き省略しである。各構成成分の寸法、形状及び配置
関係はこの発明が理解出来る程度に概略的に示しである
にすぎない。また、以下の実施例では第一導電型をp型
とし、第二導電型をn型として説明する。This will be explained with reference to the manufacturing process diagrams shown in FIGS. 1(A) to 1(H). Each figure is a sectional view showing the state of the sea urchin /\ at the main manufacturing stage, and the /\ latching that represents the cross section is omitted except for a part. The dimensions, shapes, and arrangement relationships of each component are merely shown schematically to the extent that the present invention can be understood. Further, in the following embodiments, the first conductivity type is assumed to be a p-type, and the second conductivity type is assumed to be an n-type.
この発明においては、先ず、n型GaAs予備基板lO
の」−にp型AlGaAs層!1を一回目の液相エピタ
キシャル成長工程により成長させ、第1図(A)に示す
ようなウェハを得る。この場合、予備基板IOの厚みを
約3504mとし、p型AlGaAs層11の層厚を約
300pmとする。また、この予備基板lOは後工程で
加工されて電流ブロック層とされる。また、p型AuG
aAs層llのエネルギーキャップを後述する発光のた
めの活性層の発光波長に対応するエネルギーギャップよ
りも大きく設定する。In this invention, first, an n-type GaAs preliminary substrate lO
' - p-type AlGaAs layer! 1 is grown in a first liquid phase epitaxial growth process to obtain a wafer as shown in FIG. 1(A). In this case, the thickness of the preliminary substrate IO is approximately 3504 m, and the layer thickness of the p-type AlGaAs layer 11 is approximately 300 pm. Further, this preliminary substrate IO is processed into a current blocking layer in a later process. Also, p-type AuG
The energy cap of the aAs layer 11 is set larger than the energy gap corresponding to the emission wavelength of the active layer for light emission, which will be described later.
次に、このGaAs予備基板1oの裏面側を機械的研摩
及び又は例えばアンモニア系のエツチング液での化学的
エツチングによって約10ILmの厚みにし、第1図(
B)に示すようなウェハ状態にする。ここで、以後、こ
の薄くされたGaAs予備基板を電流ブロック層12と
称し、p型AすGaAS層11が本来の基板すなわちA
uGaAs基板となる。Next, the back side of this GaAs preliminary substrate 1o is made to have a thickness of about 10 ILm by mechanical polishing and/or chemical etching with, for example, an ammonia-based etching solution, as shown in FIG.
The wafer is made into a state as shown in B). Hereinafter, this thinned GaAs preliminary substrate will be referred to as the current blocking layer 12, and the p-type A GaAs layer 11 will be referred to as the original substrate, that is, the current blocking layer 12.
This becomes a uGaAs substrate.
次に、電流ブロック層12の、面発光素子の中心を含む
その付近に、A I G a、A、s基板11に達する
深9の1円形の電流通路用の穴14を形成する(第。Next, in the vicinity of the current blocking layer 12 including the center of the surface emitting element, a circular current passage hole 14 with a depth of 9 reaching the AI Ga, A, s substrate 11 is formed (No.
l Ui!J(D))。このため、第1図(C)に示す
ように、GaAs電流ブロック層12に、その厚みの一
部分にわたる(すなわち下地のAJLGaAs基板11
に達しない)深さく例えば約51Lmの深さ)の円形の
溝16をエツチング形成する。この場合のエツチング液
を硫酸系の溶液、例えば硫#:過酸化水素:水=4:1
:1の溶液とする。続いて、このGaAs電流ブロック
層12のメルトバックを行う。lUi! J(D)). For this reason, as shown in FIG.
A circular groove 16 is etched to a depth of, for example, approximately 51 Lm (approximately 51 Lm deep). In this case, the etching solution is a sulfuric acid-based solution, for example, sulfur: hydrogen peroxide: water = 4:1.
:1 solution. Subsequently, this GaAs current blocking layer 12 is melted back.
このため、溝付きウェハを二回目の液相エピタキシャル
成長を行うための液相エピタキシャル、f&長長円内入
れる。そして、第1図([1)に示すように、このLP
E成長時に、溝16が形成されているn型GaAs電流
ブロック層12の表面を未飽和のGaAsを溶質とする
Ga溶液18に、接触させて電流ブロック層12をエツ
チングし、p型AJIGaAS基板、11の表面を露出
させる。このメルトバックを行うためのLPE成長の条
件を、例えば、H2雰囲気中で、温度を約800℃とし
、約5分間とする。For this reason, the grooved wafer is placed inside the liquid phase epitaxial, f&long ellipse for the second liquid phase epitaxial growth. As shown in FIG. 1 ([1), this LP
During E growth, the surface of the n-type GaAs current blocking layer 12 in which the grooves 16 are formed is brought into contact with a Ga solution 18 containing unsaturated GaAs as a solute to etch the current blocking layer 12, thereby forming a p-type AJI GaAS substrate. 11 surface is exposed. The LPE growth conditions for performing this meltback are, for example, a temperature of about 800° C. and a duration of about 5 minutes in an H 2 atmosphere.
このメルトバックに引き続き、同一の成長炉中における
同一のLPE成長工程で、穴14が形成されて露I11
シたAJIGaAs基板11の表面及び残存する電流ブ
ロック層12−F:、にダブルへテロ(D H)接合を
構成するp型AJljGaAsの第一クラッド層20、
p型AlGaAs活性層22及びn型AuGaAsの第
二クラッド層24を順次にLPE成長させる(第1図(
G))。Following this meltback, in the same LPE growth process in the same growth furnace, holes 14 are formed and exposed I11.
A first cladding layer 20 of p-type AJIGaAs constituting a double heterojunction (DH) on the surface of the AJIGaAs substrate 11 and the remaining current blocking layer 12-F;
A p-type AlGaAs active layer 22 and an n-type AuGaAs second cladding layer 24 are sequentially grown by LPE (see FIG.
G)).
この場合、p型AJIGaAsの第一クラッド層20は
、下地のP型AJIGaAs基板11の表面を過飽和の
Ga溶液に接触させて約2pmの厚みに成長させて、第
1図(E)に示すようなウェハ状態を得る。この時のL
PE成長条件は、H2雰囲気中で、温度を約795℃と
し、約2分間とする。In this case, the first cladding layer 20 of p-type AJIGaAs is grown to a thickness of about 2 pm by bringing the surface of the underlying p-type AJIGaAs substrate 11 into contact with a supersaturated Ga solution, as shown in FIG. 1(E). obtain a suitable wafer condition. L at this time
The PE growth conditions are an H2 atmosphere, a temperature of about 795° C., and a duration of about 2 minutes.
、 尚、このpffiAlGaAsの第一クラッド層2
0はpn接合部に注入されたキャリアを活性層22に閉
じ込める作用をする。, Incidentally, the first cladding layer 2 of this pffiAlGaAs
0 acts to confine carriers injected into the pn junction in the active layer 22.
次に、これに連続させて、このp型AIGaASの第一
クラッド層20の表面を過飽和のGa溶液に接触させて
、発光のためのp型A n G a A、sの活性層2
2を約17zmの厚みに成長させ、第1図(F)に示す
ようなウェハ状態を得る。この時のしPE成長条件は、
H2雰囲気中ア、温度を約794℃とし、約1分間とす
る。Subsequently, the surface of the first cladding layer 20 of p-type AIGaAS is brought into contact with a supersaturated Ga solution to form the active layer 2 of p-type A n Ga A,s for light emission.
2 to a thickness of about 17 zm to obtain a wafer state as shown in FIG. 1(F). The PE growth conditions at this time are:
In an H2 atmosphere, the temperature is set to about 794° C. for about 1 minute.
次に、これに連続させて、このp型AJIGaAS活性
層22の表面を過飽和のGa溶液に接触させて、n型A
JIGaAsの第二クラッド層24を、約51Lmの厚
みに、成長させ、第1図(G)、に示すようなウェハ状
態を得る。この時のLPE成長条件は、H2雰囲気中で
、温度を約793°Cとし、約5分間とする。尚、この
n型AuGaAsの第二クラッド層24はpn接合部に
注入yれたキャリアを活性層22に閉じ込める作用をす
る。Next, following this, the surface of this p-type AJI GaAS active layer 22 is brought into contact with a supersaturated Ga solution to form an n-type AJI GaAS active layer 22.
A second cladding layer 24 of JIGaAs is grown to a thickness of about 51 Lm to obtain a wafer state as shown in FIG. 1(G). The LPE growth conditions at this time are an H2 atmosphere, a temperature of about 793° C., and a duration of about 5 minutes. The second cladding layer 24 of n-type AuGaAs functions to confine carriers injected into the pn junction in the active layer 22.
その後、p型A1GaAs基板ll上に電極金属層例え
ばCr−A、u層を蒸着する。その後、Cr−Au層に
、選釈エツチング或いはリフトオフ工程によって、p側
電極2B及び光取り出し窓3oを形成する。さらに、n
型AJIGaAsの第二クラッド層24−1−に電極金
属層例えばAu−Ge−Ni合金層を蒸着してn側電極
28を形成し、第1図゛(H)に示すような半導体面発
光素子を完成する。Thereafter, an electrode metal layer, such as a Cr-A, U layer, is deposited on the p-type A1GaAs substrate 11. Thereafter, the p-side electrode 2B and the light extraction window 3o are formed in the Cr--Au layer by selective etching or a lift-off process. Furthermore, n
An electrode metal layer such as an Au-Ge-Ni alloy layer is deposited on the second cladding layer 24-1- of type AJI GaAs to form the n-side electrode 28, and a semiconductor surface emitting device as shown in FIG. complete.
この発明は−1−述した実施例にのみ限定されるもので
はない。例えば、この発明の発光素子の層構造は内部電
流ブロック層を有する層構造であれば、上述の層構造に
限定されるものではない。This invention is not limited to the embodiments described above. For example, the layer structure of the light emitting device of the present invention is not limited to the above layer structure as long as it has an internal current blocking layer.
また、−]−述した実施例で説明した数値例はこれにの
み限定されるものではなく、設計に応じて任意好適な値
に変更しても良い。Moreover, the numerical examples explained in the embodiments described above are not limited to these, and may be changed to arbitrary suitable values according to the design.
さらに、第一導電型をn導電型とし及び第二導電型をp
導電型とし、これに対応して必要な変更を行うことが出
来る。Further, the first conductivity type is an n conductivity type, and the second conductivity type is a p conductivity type.
conductivity type, and necessary changes can be made accordingly.
(発明の効果)
」二述した説明から明らかなように、この発明の半導体
面発光素子の製造方法によれば、LPE成長炉内で、G
aAs電流ブロック層に対する電流通路用の穴形成のた
めのメルトバック工程と、ダブルへテロ接合を構成する
各層の液相エピタキシャル成長を連続して行うので、G
aAs電流ブロック層の下地のA見GaAs基板の表面
が酸化されない。従って、このAuGaAs基板1−へ
の」二連の液相エピタキシャル成長を困難なく行うこと
が出来、成長された各層の結晶性が優れている。(Effects of the Invention) As is clear from the above description, according to the method for manufacturing a semiconductor surface emitting device of the present invention, G
Since the melt-back process for forming holes for current paths in the aAs current blocking layer and the liquid phase epitaxial growth of each layer constituting the double heterojunction are performed in succession, G
The surface of the A-type GaAs substrate underlying the aAs current blocking layer is not oxidized. Therefore, two consecutive liquid phase epitaxial growths can be carried out on this AuGaAs substrate 1- without difficulty, and each layer grown has excellent crystallinity.
さらに、この発明によれば、G a A s f @基
板を電流ブロック層として使用するので、製造工程が簡
単となる。Further, according to the present invention, the manufacturing process is simplified because the G a As f @ substrate is used as the current blocking layer.
Sらに、作製された素子のAJljGaAs基板は光を
吸収′しないので、n側電極で反射した光も出力として
取出すことが出来、従って、発光出力が従来よりも二倍
程度に増加する。このため、この素子は光通信だけでな
く、光情報処理の分野にも応用することが出来る。In addition, since the AJljGaAs substrate of the fabricated device does not absorb light, the light reflected by the n-side electrode can also be extracted as output, and the light emitting output is therefore increased to about twice that of the conventional device. Therefore, this element can be applied not only to optical communications but also to the field of optical information processing.
尚、この発明の方法により製造された面発光素子は、活
性層の湾曲によりレンズ効果を生じ、従って、光出力が
指向性をもち、光ファイバーとの結合効率を高める。Incidentally, the surface emitting device manufactured by the method of the present invention produces a lens effect due to the curvature of the active layer, so that the light output has directionality and the coupling efficiency with the optical fiber is increased.
第1図(A)〜(H)はこの発明の半導体面発光素子の
′製造方法を説明するための製造工程図である。
lO・・・GaAs予備基板
11・・−AuGaAs層(又はAlGaAs基板)1
2・・・GaAs電流ブロヤク層
I4・・・電流通路用の穴、 !8・・・円形の溝18
・・・Ga溶液、 20・・・第一クラッド層2
2・・・活性層、 24・・・第二クラ、ン
ド層2B・・・p側電極、 28・・・n側電極
30・・・光取り出し窓。
特許出願人 沖電気工業株式会社艷
さlさ
1へ賛 六 麺=
!−へ lへ
く ロコ −シ
Rd7−−
ロFIGS. 1A to 1H are manufacturing process diagrams for explaining the manufacturing method of the semiconductor surface emitting device of the present invention. lO...GaAs preliminary substrate 11...-AuGaAs layer (or AlGaAs substrate) 1
2...GaAs current blocking layer I4...hole for current passage, ! 8...Circular groove 18
...Ga solution, 20...first cladding layer 2
DESCRIPTION OF SYMBOLS 2...Active layer, 24...Second layer, second layer 2B...p-side electrode, 28...n-side electrode 30...light extraction window. Patent applicant Oki Electric Industry Co., Ltd.
Salsa
1 to 6 noodles=! - to l to loco -siRd7-- b
Claims (1)
s予備基板上に第一導電型のAlGaAs層を成長させ
る工程と、 該予備基板に電流通路用の穴を形成するための、液相エ
ピタキシャル成長のメルトバック工程と、 該メルトバック工程に引き続き、前記穴付き電流ブロッ
ク層上に、ダブルヘテロ接合を形成する第一クラッド層
、活性層及び第二クラッド層を順次に液相エピタキシャ
ル成長させる工程と を含むことを特徴とする半導体面発光素子の製造方法。(1) Second conductivity type GaA used as current blocking layer
a step of growing an AlGaAs layer of the first conductivity type on the preliminary substrate; a meltback step of liquid phase epitaxial growth for forming a hole for a current path in the preliminary substrate; and subsequent to the meltback step, A method for manufacturing a semiconductor surface emitting device, comprising the step of sequentially growing a first cladding layer, an active layer, and a second cladding layer forming a double heterojunction by liquid phase epitaxial growth on a current blocking layer with holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60123072A JPS61281561A (en) | 1985-06-06 | 1985-06-06 | Manufacture of semiconductor-surface light-emitting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60123072A JPS61281561A (en) | 1985-06-06 | 1985-06-06 | Manufacture of semiconductor-surface light-emitting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61281561A true JPS61281561A (en) | 1986-12-11 |
Family
ID=14851493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60123072A Pending JPS61281561A (en) | 1985-06-06 | 1985-06-06 | Manufacture of semiconductor-surface light-emitting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61281561A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4921817A (en) * | 1987-07-09 | 1990-05-01 | Mitsubishi Monsanto Chemical Co. | Substrate for high-intensity led, and method of epitaxially growing same |
| US5913130A (en) * | 1996-06-12 | 1999-06-15 | Harris Corporation | Method for fabricating a power device |
| JP2012015154A (en) * | 2010-06-29 | 2012-01-19 | Ngk Insulators Ltd | Semiconductor light-emitting device and method for manufacturing the same |
-
1985
- 1985-06-06 JP JP60123072A patent/JPS61281561A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4921817A (en) * | 1987-07-09 | 1990-05-01 | Mitsubishi Monsanto Chemical Co. | Substrate for high-intensity led, and method of epitaxially growing same |
| US5913130A (en) * | 1996-06-12 | 1999-06-15 | Harris Corporation | Method for fabricating a power device |
| US6078077A (en) * | 1996-06-12 | 2000-06-20 | Intersil Corporation | Power device |
| US6236083B1 (en) | 1996-06-12 | 2001-05-22 | Intersil Corporation | Power device |
| JP2012015154A (en) * | 2010-06-29 | 2012-01-19 | Ngk Insulators Ltd | Semiconductor light-emitting device and method for manufacturing the same |
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