JPS6128227B2 - - Google Patents
Info
- Publication number
- JPS6128227B2 JPS6128227B2 JP49079669A JP7966974A JPS6128227B2 JP S6128227 B2 JPS6128227 B2 JP S6128227B2 JP 49079669 A JP49079669 A JP 49079669A JP 7966974 A JP7966974 A JP 7966974A JP S6128227 B2 JPS6128227 B2 JP S6128227B2
- Authority
- JP
- Japan
- Prior art keywords
- surface acoustic
- region
- acoustic wave
- integrated circuit
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010897 surface acoustic wave method Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 description 26
- 239000010408 film Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009429 electrical wiring Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 gallium arsenide compound Chemical class 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Pressure Sensors (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
【発明の詳細な説明】
本発明は弾性表面波素子を一体化して含んだ半
導体集積回路装置の新規なる構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure of a semiconductor integrated circuit device that integrally includes a surface acoustic wave element.
従来の半導体集積回路においては、コイルやコ
ンデンサを含む共振回路はその中に一体化して実
現することが出来ず、同調回路やフイルタ回路な
どは半導体集積回路から端子を出して外部で接続
する手段がとられて来た。このため、高周波回路
等に於いては集積密度が上らず、パツケージの端
子数のみ徒らに増加して機器の小型化に対する要
求を充分に満すことが出来なかつた。 In conventional semiconductor integrated circuits, resonant circuits including coils and capacitors cannot be integrated into the circuit, and tuning circuits, filter circuits, etc. cannot be connected externally by extending terminals from the semiconductor integrated circuit. It was taken. For this reason, the integration density of high-frequency circuits and the like has not increased, and the number of terminals on the package has increased unnecessarily, making it impossible to satisfactorily meet the demand for miniaturization of equipment.
一方、電気的共振現象を機械的共振におきかえ
た電気振動素子は単体としてすぐれた特性が得ら
れるものの、電気機械変換子の構造や振動体の保
持機構が複雑であり集積回路に一体化することは
困難とされてきた。しかし、最近弾性表面波振動
を応用した素子で高性能のフイルタなどを実現す
る試みがなされている。弾性表面波を利用する場
合には保持機構は簡単になるが、弾性表面波は進
行波であるため電気機械変換損失が比較的大きく
損失を補うために通常その入力及び出力増巾回路
は別個に集積回路又は個別の素子等を追加しなけ
ればならず、小型化及び集積回路のパツケージ端
子数の減少は以然としてなされなかつた。 On the other hand, although an electric vibrating element that replaces the electrical resonance phenomenon with mechanical resonance can obtain excellent characteristics as a single unit, the structure of the electromechanical transducer and the holding mechanism of the vibrating body are complicated, and it is difficult to integrate it into an integrated circuit. has been considered difficult. However, recently, attempts have been made to realize high-performance filters and the like using elements that apply surface acoustic wave vibration. When using surface acoustic waves, the holding mechanism becomes simple, but since surface acoustic waves are traveling waves, electromechanical conversion losses are relatively large, and input and output amplification circuits are usually separate to compensate for the losses. Since integrated circuits or individual components must be added, miniaturization and reduction in the number of integrated circuit package terminals have not been achieved.
本発明はかかる半導体集積回路に弾性表面波素
子を含んで一体化構造とした新規な構造を提供せ
んとするものであり、その目的とするところは前
記共振回路を含む回路の小型化であり、更に他の
目的は一体化することにより、集積回路の端子数
の減少及び従来の結線接続をなくすることによる
組立コストの軽減と信頼性の増加にある。 The present invention aims to provide a novel structure in which a surface acoustic wave element is integrated into such a semiconductor integrated circuit, and its purpose is to miniaturize the circuit including the resonant circuit, Yet another objective is to reduce assembly costs and increase reliability by reducing the number of terminals on an integrated circuit and eliminating traditional wire connections.
更に他の目的は、一体化することにより弾性表
面波素子の特性を安定化するものである。この発
明によれば半導体基板内にPN接合の組み合せに
よつて構成されたトランジスタ、ダイオード又は
抵抗及び容量等を含み、この基板の一主表面に更
に圧電薄膜を含んで構成された弾性表面波素子を
形成し、前記基板内の各々の素子と基板表面の弾
性表面波素子とを配線接続した一体化された半導
体集積回路装置が得られる。 Still another object is to stabilize the characteristics of the surface acoustic wave element by integrating the elements. According to the present invention, a surface acoustic wave element includes a transistor, a diode, a resistor, a capacitor, etc. configured by a combination of PN junctions in a semiconductor substrate, and further includes a piezoelectric thin film on one main surface of the substrate. An integrated semiconductor integrated circuit device is obtained in which each element in the substrate and the surface acoustic wave element on the surface of the substrate are connected by wiring.
次にこの発明の特徴をより良く理解するために
本発明の具体的な実施例につき図を用いて説明を
加える。 Next, in order to better understand the features of the present invention, specific embodiments of the present invention will be explained using figures.
第1図は本発明の第1の実施例を示す上面構成
図であり第2図は第1図―′線に沿つた断面
図である。図に於いて1は10〜20Ω―cmのP型シ
リコン基板であり、この所定領域にn+埋込拡散
層2が設けられた後、比抵抗1Ω―cm、厚さ12ミ
クロンのn型エピタキシヤル成長層が形成され、
周知の選択拡散技術でp+型分離拡散領域3によ
つてエピタキシヤル成長層は分離された島領域4
及び5となる。島領域4には集積回路用トランジ
スタが構成される。即ち、p型ベース領域6及び
n+型エミツタ領域7が形成され、エミツタ領域
の形成と同時にコレクタコンタクトn+領域8も
形成される。表面の保護用絶縁膜9は通常窒化硅
素膜や酸化硅素膜又は金属酸化膜が用いられる。
この絶縁膜9は弾性表面波素子を構成すべき領域
に於いては、通常静電容量を減少させるために厚
い絶縁膜9′となつている。 FIG. 1 is a top configuration diagram showing a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line 1--' in FIG. In the figure, 1 is a P-type silicon substrate with a resistance of 10 to 20 Ω-cm, and after an n + buried diffusion layer 2 is provided in a predetermined region, an n-type epitaxial layer with a resistivity of 1 Ω-cm and a thickness of 12 microns is formed. A growth layer is formed,
The epitaxial growth layer is separated by an island region 4 by a p + type isolation diffusion region 3 using a well-known selective diffusion technique.
and 5. In the island region 4, integrated circuit transistors are formed. That is, the p-type base region 6 and
An n + type emitter region 7 is formed, and a collector contact n + region 8 is also formed simultaneously with the formation of the emitter region. The protective insulating film 9 on the surface is usually a silicon nitride film, a silicon oxide film, or a metal oxide film.
This insulating film 9 is usually a thick insulating film 9' in a region where a surface acoustic wave element is to be formed in order to reduce capacitance.
そして島領域4に構成されたトランジスタ及び
他の島領域(図示せず)の各種素子と弾性表面波
素子の櫛形電極10及び11を電気的に接続する
金属薄膜の電気配線12と、前記櫛歯状変換電極
10が金属薄膜の蒸着と写真食刻法によつて同時
に構成される。さらに櫛波状変換電極10の上部
に弾性表面波変換用の圧電薄膜であるZnO13が
厚さ約1.2ミクロンにスパツタリングにより選択
的に被着され、更にその上部に対向電極として金
属薄膜14が形成され本発明の一実施例の一体化
した半導体装置が得られる。 Then, electrical wiring 12 made of a thin metal film electrically connects the comb-shaped electrodes 10 and 11 of the surface acoustic wave device to the transistor configured in the island region 4 and various elements in other island regions (not shown), and the comb teeth. The state conversion electrode 10 is constructed simultaneously by vapor deposition of a metal thin film and photolithography. Furthermore, ZnO 13, which is a piezoelectric thin film for surface acoustic wave conversion, is selectively deposited on the top of the comb-wave conversion electrode 10 to a thickness of about 1.2 microns by sputtering, and a metal thin film 14 is further formed as a counter electrode on top of the ZnO film 13, which is a piezoelectric thin film for surface acoustic wave conversion. An integrated semiconductor device according to an embodiment of the invention is obtained.
さてこの装置において、集積回路を構成する入
力端子より入つた信号は集積回路中の増巾器で適
当な振巾に増巾され、(第1図ではその1部が島
領域4の集積回路用トランジスタとして示されて
いる)電気信号―弾性表面波のトランスデユーサ
の櫛歯状変換電極10に電気配線12を介して加
えられる。圧電物質であるZnO薄膜13を電気的
に励振して信号が弾性表面波に変換されると、も
う一方の櫛歯状変換電極11を励振し、電気信号
に再び変換されてとり出され再び電気配線(図示
せず)によつて集積回路へと導かれる。 Now, in this device, the signal input from the input terminal that constitutes the integrated circuit is amplified to an appropriate amplitude by the amplifier in the integrated circuit (in Fig. 1, a part of the signal is used for the integrated circuit in the island area 4). An electrical signal (shown as a transistor) is applied via electrical wiring 12 to the comb-like transducer electrode 10 of a surface acoustic wave transducer. When the ZnO thin film 13, which is a piezoelectric material, is electrically excited and the signal is converted into a surface acoustic wave, the other comb-shaped conversion electrode 11 is excited, and the signal is converted back into an electric signal, taken out, and generated again. Wiring (not shown) leads to the integrated circuit.
弾性表面波の周波数と音速から弾性表面波の波
長が定まるがこの波長が櫛形電極のピツチに一致
した時に電気信号と弾性表面波が同期し、電気信
号―弾性表面波の変換効率が最高となる。この周
波数がフイルタの中心周波数に相当する。 The wavelength of the surface acoustic wave is determined from the frequency of the surface acoustic wave and the speed of sound. When this wavelength matches the pitch of the comb-shaped electrode, the electrical signal and the surface acoustic wave are synchronized, and the conversion efficiency between the electrical signal and the surface acoustic wave is the highest. . This frequency corresponds to the center frequency of the filter.
本実施例では島領域4のコレクタ領域にn+埋
込拡散層2が設けられているが、これは通常コレ
クタ抵抗を減少させる目的であり場合によつては
省略することがあるのは周知のとおりである。 In this embodiment, an n + buried diffusion layer 2 is provided in the collector region of the island region 4, but it is well known that this is usually for the purpose of reducing collector resistance and may be omitted in some cases. That's right.
また、弾性表面波素子の対向電極14も要求す
る電気的特性によつては省略しても構わない。そ
してトランスデユーサの構成方法としては上下が
逆の形の構成も可能であつて、即ち絶縁膜9の表
面に金属配線12と同時に対向電極14を先に形
成し、その上に圧電物質の薄膜ZnO13を被着し
た後その上面に櫛形電極10及び11を形成する
か、対向電極14を形成しZnO13を被着した後
に金属配線12及び櫛形電極10,11を同時に
形成することも可能であり、この場合に半導体基
板の導電性を利用して対向電極14を省くことも
できる。 Further, the counter electrode 14 of the surface acoustic wave element may also be omitted depending on the required electrical characteristics. As for the construction method of the transducer, it is also possible to construct the transducer upside down, that is, to first form the counter electrode 14 on the surface of the insulating film 9 at the same time as the metal wiring 12, and then to form a thin film of piezoelectric material on top of the counter electrode 14. It is also possible to form the comb-shaped electrodes 10 and 11 on the top surface after depositing ZnO 13, or to form the metal wiring 12 and the comb-shaped electrodes 10 and 11 at the same time after forming the counter electrode 14 and depositing ZnO 13. In this case, the counter electrode 14 can be omitted by utilizing the conductivity of the semiconductor substrate.
更に上述の実施例の説明では集積回路トランジ
スタの島領域4と弾性表面波素子部の島領域5を
それぞれシリコン基板1の別領域に設けた例につ
いて説明したが、シリコン基板面積を減少させる
目的でシリコン基板内に構成した集積回路用の各
素子の表面に絶縁膜9を介して櫛形電極10及び
11と圧電物質のZnO薄膜13を設け、基板内集
積回路上に弾性表面波素子を形成した構造も可能
なことはいうまでもない。 Furthermore, in the explanation of the above embodiment, an example was explained in which the island region 4 of the integrated circuit transistor and the island region 5 of the surface acoustic wave element section were provided in separate regions of the silicon substrate 1, but for the purpose of reducing the silicon substrate area. A structure in which comb-shaped electrodes 10 and 11 and a piezoelectric ZnO thin film 13 are provided on the surface of each element for an integrated circuit configured in a silicon substrate via an insulating film 9, and a surface acoustic wave element is formed on the integrated circuit in the substrate. Needless to say, it is possible.
第3図は本発明の第2の実施例を示す断面図で
あつて弾性表面波の櫛形電極から半導体基板への
静電容量を減少するため、該電極下部にPN接合
を設け、接合容量が直列接続されることにより綜
合容量を減少させ、高周波信号に対する特性の改
善を試みたものである。即ち図に於いて理解を明
解にするため、第1の実施例と共通の部分につい
ては共通の番号を用いて説明すると、先ず半導体
基板1としてはp型10〜20Ω―cmのシリコン結晶
を準備する。前記第1の実施例では基板表面に埋
込拡散層を設けた説明をおこなつたが、本発明の
本旨とは直接関係ないのでこれを省略すると、次
にn型1Ω―cmのエピタキシヤル成長層が基板1
の主表面に形成され、p+型分離拡散層3によつ
てエピタキシヤル成長層は分離された島領域4及
び5となる。島領域4には集積回路用トランジス
タとしてp型のベース領域6,n+型エミツタ領
域7及びこれと同時にコレクタコンタクトn+領
域8が形成されるが、ベース領域6の形成時にこ
れと同時に島領域5の弾性表面波素子の櫛形電極
10及び11の下部にp+拡散領域15及び16
を形成する。9は表面保護用の絶縁膜であり、絶
縁膜9の表面上に金属薄膜による電気配線12及
び櫛歯状の変換電極10と11が構成される。櫛
形電極10及び11は前記p+型拡散領域15及
び16の上部に絶縁膜9を介して位置するが、こ
の領域のみ絶縁膜を選択的に除去し、櫛形電極1
0及び11が直接p+拡散領域15及び16の表
面に電気的に接続されて配置することも可能であ
る。そのいづれをとるかは、要求する電気特性に
依存するが、全体の集積回路を構成する電気回路
の結線及びバイアス電圧等によつても制約を受け
る。櫛形電極10及び11の上部には圧電物質と
してZnO13が厚さ約1.2ミクロンにスパツタリ
ングによつて選択的に被着される。更に該圧電物
質内に電界集中効果を大ならしむるにその上部に
対向電極14を構成するが、第1の実施例で述べ
た様にこれは省略することも又は一方の変換電極
10と他方の櫛形電極11との中間の位置に遮蔽
効果をもたせて配置することもあるし、対向電極
14の形状や電極配線12との接続等に種々の方
法が考えられるが前述したように本発明の本旨で
はないので詳細な説明は省略する。 FIG. 3 is a cross-sectional view showing a second embodiment of the present invention. In order to reduce the capacitance from the surface acoustic wave comb-shaped electrode to the semiconductor substrate, a PN junction is provided at the bottom of the electrode, and the junction capacitance is reduced. This is an attempt to reduce the combined capacitance by connecting them in series and improve the characteristics for high frequency signals. That is, in order to make the understanding clear in the diagram, parts common to those in the first embodiment will be explained using common numbers. First, a p-type silicon crystal of 10 to 20 Ω-cm is prepared as a semiconductor substrate 1. do. In the first embodiment, a description was given of providing a buried diffusion layer on the substrate surface, but since it is not directly related to the main purpose of the present invention, this will be omitted.Next, we will explain the epitaxial growth of n-type 1Ω-cm layer is substrate 1
The epitaxial growth layer becomes island regions 4 and 5 separated by the p + type isolation diffusion layer 3 . In the island region 4, a p-type base region 6, an n + -type emitter region 7, and a collector contact n + region 8 are formed as a transistor for an integrated circuit. P + diffusion regions 15 and 16 are provided below the comb-shaped electrodes 10 and 11 of the surface acoustic wave element No. 5.
form. Reference numeral 9 denotes an insulating film for surface protection, and on the surface of the insulating film 9, electrical wiring 12 made of a metal thin film and comb-shaped conversion electrodes 10 and 11 are formed. The comb-shaped electrodes 10 and 11 are located above the p + -type diffusion regions 15 and 16 with an insulating film 9 in between.
It is also possible to arrange that 0 and 11 are electrically connected directly to the surfaces of p + diffusion regions 15 and 16. Which of these is chosen depends on the required electrical characteristics, but is also constrained by the wiring and bias voltage of the electrical circuits constituting the entire integrated circuit. On top of the comb-shaped electrodes 10 and 11, ZnO 13 as a piezoelectric material is selectively deposited to a thickness of about 1.2 microns by sputtering. Furthermore, a counter electrode 14 is formed on the top of the piezoelectric material to increase the electric field concentration effect within the piezoelectric material, but as described in the first embodiment, this may be omitted, or one transducer electrode 10 and the other transducer electrode 14 may be omitted. It may be placed at a position intermediate to the comb-shaped electrode 11 with a shielding effect, and various methods can be considered for the shape of the counter electrode 14 and the connection with the electrode wiring 12, but as described above, the main purpose of the present invention Since this is not the case, a detailed explanation will be omitted.
更に第4図及び第5図に従つて本発明の第3の
実施例について説明する。第4図は本発明の第3
の実施例を示す上面構成図、第5図は第4図の破
線―′線に沿つた断面図である。前述の実施
例と同様にp型10〜20Ω―cmのシリコン基板1に
n型1Ω―cmのエピタキシヤル結晶成長を約12ミ
クロンおこなつた後、表面より選択拡散技術によ
りp+型の分離拡散領域3を形成してエピタキシ
ヤル成長層をそれぞれ独立したn型の島領域4及
び5とする。島領域4には集積回路用トランジス
タとしてp型のベース領域6,n+型エミツタ領
域7及びこれと同時にコレクタコンタクトn+領
域8が形成されるが、ベース領域6の形成時にこ
れと同時に島領域5内にも電気信号―弾性表面波
変換電極となるべきp+拡散領域17及び18を
形成する。 Further, a third embodiment of the present invention will be described with reference to FIGS. 4 and 5. Figure 4 shows the third embodiment of the present invention.
FIG. 5 is a sectional view taken along the dashed line -' in FIG. 4. As in the previous example, after growing an n-type 1 Ω-cm epitaxial crystal to a thickness of about 12 microns on a p-type 10 to 20 Ω-cm silicon substrate 1, p + type was separated and diffused from the surface using selective diffusion technology. Region 3 is formed to form the epitaxial growth layer into independent n-type island regions 4 and 5, respectively. In the island region 4, a p-type base region 6, an n + -type emitter region 7, and a collector contact n + region 8 are formed as a transistor for an integrated circuit. P + diffusion regions 17 and 18, which are to serve as electrical signal-to-surface acoustic wave conversion electrodes, are also formed within 5.
第5図から明確なように櫛形電極用のp+拡散
領域17の端部19は基板表面の絶縁膜9(第5
図では図示されていない)上の金属薄膜による電
気配線12によつて島領域4の集積回路トランジ
スタのベース領域6に接続される。絶縁膜9が形
成され、金属薄膜の電気配線12が形成された
後、櫛形電極用のp+型拡散領域17及び18の
上部領域に圧電物質であるZnO薄膜13がスパツ
タリングにより約1.2ミクロン被着されて弾性表
面波トランスデユーサを含んで一体化された集積
回路が得られる。 As is clear from FIG. 5, the end portion 19 of the p + diffusion region 17 for the comb-shaped electrode is
The island region 4 is connected to the base region 6 of the integrated circuit transistor by an electrical thin film electrical interconnect 12 on top (not shown in the figure). After the insulating film 9 is formed and the metal thin film electrical wiring 12 is formed, a ZnO thin film 13 of about 1.2 microns, which is a piezoelectric material, is deposited by sputtering on the upper regions of the p + -type diffusion regions 17 and 18 for the comb-shaped electrodes. An integrated integrated circuit including a surface acoustic wave transducer is obtained.
本実施例では弾性表面波―電気信号またはその
逆の変換電極を前述の第1及び第2の実施例と異
なり、金属薄膜で構成するのと異なり半導体基板
内の不純物拡散領域そのものを用いている点であ
つて、ここにあげた例ではベース領域6の形成時
に同時に形成されるp型不純物拡散領域を用いて
いるが、島領域5内に更にp型の島領域を形成
し、その中に高濃度n+拡散によつて櫛歯状の変
換電極を構成させることも出来る。また、同様に
p+型拡散領域17及び18を集積回路用トラン
ジスタのベース領域6の選択拡散とは別個に高濃
度のp+型拡散で形成することも当然可能であ
る。 In this embodiment, unlike the first and second embodiments described above, the conversion electrode for converting surface acoustic waves to electric signals or vice versa is made of an impurity diffusion region itself in the semiconductor substrate, unlike the first and second embodiments, in which the conversion electrode is made of a metal thin film. In the example given here, a p-type impurity diffusion region formed at the same time as the base region 6 is used, but a p-type island region is further formed within the island region 5, and a p-type impurity diffusion region is formed within the island region 5. A comb-shaped conversion electrode can also be constructed by high-concentration n + diffusion. Also, similarly
Of course, it is also possible to form the p + -type diffusion regions 17 and 18 by high-concentration p + -type diffusion separately from the selective diffusion of the base region 6 of the integrated circuit transistor.
この様に変換電極を半導体基板内の拡散領域で
形成することによつて圧電物質としてのZnO薄膜
13内の電極による凹凸をなくし、不用の弾性波
の発生による特性の悪化を減少させることが出来
る。また、拡散領域17,18に適当なバイアス
電圧を印加することにより、PN接合の逆バイア
スによる接合容量の減少をはかり、基板への等価
的な静電容量を減少して高周波特性を向上させる
ことが出来、さらに基板と拡散よりなる櫛形電極
とは音速や膨張係数はほぼ等しいので電極境界面
での弾性表面波の反射が少なく、温度変化に対し
ても安定で信頼性が高いという特徴を有する。 By forming the conversion electrode in the diffusion region in the semiconductor substrate in this way, it is possible to eliminate the unevenness caused by the electrode in the ZnO thin film 13 as a piezoelectric material, and to reduce the deterioration of characteristics due to the generation of unnecessary acoustic waves. . Furthermore, by applying an appropriate bias voltage to the diffusion regions 17 and 18, the junction capacitance due to reverse bias of the PN junction can be reduced, and the equivalent capacitance to the substrate can be reduced to improve high frequency characteristics. Furthermore, since the sound velocity and expansion coefficient of the comb-shaped electrode made of the substrate and diffusion are almost the same, there is little reflection of surface acoustic waves at the electrode interface, and it is stable and highly reliable against temperature changes. .
以上述べたごとく本発明によつて弾性表面波素
子を含めた一体化された半導体集積回路がはじめ
て達成され、電子回路の小型化が著るしく進行し
集積密度の向上がなされると共に、端子数の減少
及び組立工数の軽減からくるコスト低減と信頼性
の向上及び一体化することによつて初めて達成さ
れる高周波特性の向上と安定化等、限りない効果
をもたらすことが可能となつた。 As described above, by the present invention, an integrated semiconductor integrated circuit including a surface acoustic wave element has been achieved for the first time, and the miniaturization of electronic circuits has progressed significantly, the integration density has been improved, and the number of terminals has increased. It has become possible to bring about limitless effects, such as cost reduction and improved reliability due to the reduction in the number of components and assembly man-hours, and the improvement and stabilization of high frequency characteristics that can only be achieved by integrating them.
本発明の実施例に於いては、弾性表面波素子を
フイルタとして利用した例をとりあげて説明した
が、電極の位置を適当に選ぶことによつて遅延素
子とした場合は勿論、一般のトランスデユーサと
して応用する場合にも本発明の本旨を適用するこ
とが出来ることは明らかである。 In the embodiments of the present invention, an example in which a surface acoustic wave element is used as a filter has been explained, but it can also be used as a delay element by appropriately selecting the electrode positions, and it can also be used as a general transducer. It is clear that the gist of the present invention can also be applied to applications as a user.
以上の実施例の説明においては簡単化のために
集積回路として増幅器、弾性表面波素子としてフ
イルタ、圧電薄膜としてZnO薄膜を用いた場合に
ついて説明をしたが、他に遅延線、弾性表面波の
非線形性や光偏向作用を応用した信号処理を行う
弾性表面波素子を用いたり、圧電薄膜として他に
ZnS,CdSなども利用でき、これらを組合せてな
る他の機能を有する半導体集積回路の構成も可能
であり、勿論これらの本発明の範囲に含まれるも
のである。 In the above embodiments, for the sake of simplicity, we have explained the case where an amplifier is used as an integrated circuit, a filter is used as a surface acoustic wave element, and a ZnO thin film is used as a piezoelectric thin film. We use surface acoustic wave devices that perform signal processing by applying optical properties and optical deflection effects, and other methods such as piezoelectric thin films.
ZnS, CdS, etc. can also be used, and it is also possible to construct a semiconductor integrated circuit having other functions by combining these materials, and these are, of course, included in the scope of the present invention.
また、半導体基板としてp型シリコン結晶を用
いた場合について述べたが、すべての構成につい
て逆の導電型を適用した場合にも本発明は成立す
る。更に半導体結晶基板としてはシリコンの他に
ゲルマニウム、及び砒化ガリウム等―族化合
物半導体結晶にも適用できる。 Further, although the case where a p-type silicon crystal is used as the semiconductor substrate has been described, the present invention also works when the opposite conductivity type is applied to all the structures. Further, as the semiconductor crystal substrate, in addition to silicon, germanium and gallium arsenide compound semiconductor crystals can also be used.
また、本発明の実施例としては集積回路の島領
域の形成に、分離拡散方式を用いた場合を説明し
たが、他の分離方式の場合にも全く同様に本発明
を適用することが出来る。 Further, although the embodiment of the present invention has been described in which a separation/diffusion method is used to form an island region of an integrated circuit, the present invention can be applied in exactly the same manner to other isolation methods.
第1図は本発明の第1実施例半導体集積回路装
置を示す上面構成図、第2図は第1図の破線―
′線に沿つた断面図、第3図は本発明の第2の
実施例の装置を示す断面図、第4図は本発明の第
3の実施例の装置を示す上面構成図、第5図は第
4図の―′線に沿つた断面図である。
1…半導体基板、3…分離拡散層、4,5…島
領域、10,11…櫛形電極、12…金属配線、
13…圧電物質薄膜、15,16,17,18…
拡散領域。
FIG. 1 is a top configuration diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a broken line shown in FIG. 1.
3 is a cross-sectional view showing the device of the second embodiment of the present invention, FIG. 4 is a top configuration diagram showing the device of the third embodiment of the present invention, and FIG. is a sectional view taken along the line -' in FIG. 4; DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Separation diffusion layer, 4, 5... Island region, 10, 11... Comb-shaped electrode, 12... Metal wiring,
13... Piezoelectric material thin film, 15, 16, 17, 18...
Diffusion area.
Claims (1)
る半導体基板の一主表面上に、少なくとも圧電薄
膜を含んで構成される弾性表面波素子を形成した
ことを特徴とする半導体集積回路装置。 2 前記半導体基板の一主表面上の所定領域に、
この所定領域と反対導電形の領域を形成し、前記
所定領域上に金属電極を介して前記弾性表面波素
子を設置したことを特徴とする特許請求の範囲第
1項に記載の半導体集積回路装置。 3 前記半導体基板の一主表面上の所定領域にこ
の所定領域と反対導電形の領域を形成し、この反
対導電形の領域を前記弾性表面波素子における弾
性表面波と電気信号の変換電極として用いたこと
を特徴とする特許請求の範囲第1項に記載の半導
体集積回路装置。[Scope of Claims] 1. A semiconductor characterized in that a surface acoustic wave element including at least a piezoelectric thin film is formed on one main surface of a semiconductor substrate having a plurality of island regions including active or passive elements. Integrated circuit device. 2. In a predetermined region on one main surface of the semiconductor substrate,
A semiconductor integrated circuit device according to claim 1, wherein a region having a conductivity type opposite to the predetermined region is formed, and the surface acoustic wave element is disposed on the predetermined region via a metal electrode. . 3. A region having a conductivity type opposite to that of the predetermined region is formed in a predetermined region on one main surface of the semiconductor substrate, and the region having the opposite conductivity type is used as a conversion electrode for surface acoustic waves and electric signals in the surface acoustic wave element. A semiconductor integrated circuit device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49079669A JPS5112780A (en) | 1974-07-10 | 1974-07-10 | Handotaishusekikairosochi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP49079669A JPS5112780A (en) | 1974-07-10 | 1974-07-10 | Handotaishusekikairosochi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5112780A JPS5112780A (en) | 1976-01-31 |
| JPS6128227B2 true JPS6128227B2 (en) | 1986-06-28 |
Family
ID=13696572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49079669A Granted JPS5112780A (en) | 1974-07-10 | 1974-07-10 | Handotaishusekikairosochi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5112780A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6276438U (en) * | 1985-10-31 | 1987-05-16 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5412544A (en) * | 1977-06-29 | 1979-01-30 | Toshiba Corp | Elastic surface wave unit |
| JPS596610A (en) * | 1982-07-02 | 1984-01-13 | Clarion Co Ltd | Elastic surface wave device |
| JPH0324719U (en) * | 1990-07-12 | 1991-03-14 |
-
1974
- 1974-07-10 JP JP49079669A patent/JPS5112780A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6276438U (en) * | 1985-10-31 | 1987-05-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5112780A (en) | 1976-01-31 |
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