JPS6129073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS memory circuit, such as a dynamic MIS (metal-insulator-semiconductor) memory circuit, in which word lines are driven by timing signals.

Dynamic MIS memory circuits utilize the presence or absence of charge accumulated in a storage capacity.

Writing to this storage capacity is done via a switching MISFET controlled by the word line, so when writing information at the power supply voltage level,
The charging voltage level decreases by the threshold voltage of this MISFET (when the write level and the word line control level are the same).

For this reason, especially in dynamic MIS memory circuits that directly read out the stored storage level, such as dynamic MIS memory circuits consisting of one-transistor memory cells, consideration is given to increasing the power supply voltage to compensate for the voltage loss. There is. Therefore, a dynamic MIS memory circuit that operates at a low power supply voltage (for example, about 5V) could not be put into practical use.

Note that the circuit for driving the word or bit line of a monolithic memory is described in Japanese Patent Application Laid-Open No. 1986-
It is shown in Publication No. 52938.

This invention was made in order to provide a dynamic MIS memory circuit that prevents voltage loss in switching MISFETs that constitute memory cells.

Hereinafter, the present invention will be specifically explained with reference to Examples.

FIG. 1 is a circuit diagram showing a main part of a dynamic MIS memory which is an embodiment of the present invention.

Reference numeral 1 denotes a word clock generating circuit, which forms a selection pulse for the word line W. This circuit generates the word clock _XWC at the timing when the address information _a0 to _a5 is determined, so the drive MISFET _Q5 , which is kept in an on state by the charge precharged during the chip non-selection period, is activated by the address information a. At the rising edge of either ₀ or ₀ , MISFETQ ₂ or
By turning _Q3 on, it is turned off and word clock _XWC is generated.

That is, the word clock generation circuit includes a detection circuit that detects changes in address information, and generates a word clock _XWC in response to changes in address information.

2 shows a part of the row-related address decoder circuit group. In this figure, two X-based address decoders are shown for convenience of explanation. Address information a ₁ ,
₁ is established, and if the address inputs of MISFETQ ₉ to Q ₁₁ are all at low level, the address decoder made up of these MISFETs will be driven.
MISFETQ ₈ turns on. In this way, the word clock _XWC applied to the drain is output to the source side, making the word line _W1 high level.

At this time, the drive MISFETs other than _Q8 of the X-system address decoder circuit group are turned off.

A bootstrap capacitor is provided between the gate and source of the word line drive MISFETs Q ₈ and Q ₁₄ , and by making the gate voltage higher than the drain voltage, it is considered that the drain voltage is directly output to the source side.

The write/read MISFETs Q ₂₀ and Q ₂₁ of the memory cells 4 and 4' whose gates are connected to the selected word line (W ₁ in the above example) are turned on when the word clock X _WC is applied. For example, when writing a high level, the high level of the digit line is written to the storage capacitors C _S1 and C _S2 via the MISFETs Q ₂₀ and Q ₂₁ .

At this time, if the voltage level of the digit line≈the voltage level of the word line, the write voltage will be the word line voltage level - the threshold voltage of _MISFETQ20 , _Q21 . Therefore, when the write level is lowered and discharge due to leakage current of the storage capacitor C _S is taken into account, it becomes difficult to operate the memory under a low power supply voltage as described above.

Therefore, in this embodiment, the delay circuit 3 and the bootstrap capacitance C _BI are designed to prevent write voltage loss due to the threshold voltage of the switching MISFET of the memory cell.

In other words, the word clock
Timing signal X _W delayed by a predetermined time t _d from _WC
A bootstrap capacitor C _BI forms _C ' and one end is connected to the output terminal of the word clock generation circuit 1.
The timing signal X _WC ' is applied to the other end of the signal.

As a result, as shown in FIG. 2, the parasitic capacitance C _ST and bootstrap capacitance at this output terminal are charged by the word clock X _WC that rises at the rising edge of the address information a ₀ or ₀ , and then the timing signal X _WC ' At the rising edge of , the other end of the bootstrap capacitor is lifted, so the voltage level of the word clock increases by ΔV.

This voltage ΔV is determined by charge division based on the capacitance ratio of the capacitors C _ST and C _BI and is obtained by the following equation (1).

ΔV=C _BI /C _ST +C _BI Vφ (1) where Vφ is the voltage level of the word clock and timing signals.

Therefore, if Vφ = 4.5V and _CST = _CBI , ΔV becomes 2.25V, and due to this bootstrap effect, the voltage level of the word clock _XWC at this time can be raised to about 6.75V, Because the word line drive MISFET outputs the word clock voltage, which is the drain voltage, directly to the source side due to its bootstrap effect, the gate voltage of the memory cell write/read MISFET is a value sufficient to operate this MISFET in a non-saturated manner. The voltage of the digit line becomes higher than that of the digit line, and the voltage of the digit line is transmitted to the storage capacitor without voltage loss.

The delay circuit 3 is a dynamic inverter.
Q ₂₄ , Q ₂₅ and Q ₂₆ , Q ₂₇ are connected in series, and the delay time t _d of this circuit should be set at least to the time required for the rise of the word clock X _WC to enhance the bootstrap effect. preferred above. This will be easily understood from the above explanation of the operation. This time setting can be adjusted by the conductance of the MISFET of the inverter.

According to the circuit of this embodiment described above, the writing level to the memory cell can be increased simply by adding the delay circuit 3 and the capacitor.

Along with this, it is also possible to lower the power supply voltage of the memory circuit, which not only makes connection with the TTC circuit easier, but can also be expected to significantly reduce power consumption.

This invention is not limited to the above embodiments, and can take various embodiments.

As the bootstrap capacitance C _BI is increased against the parasitic capacitance in the word clock output line, the voltage can be increased as is clear from equation (1), but on the other hand, the rise of the word clock becomes slower. , it is desirable to choose the minimum value required.

Furthermore, the delay circuit 3 can be modified in various ways, such as one using a transmission gate MISFET.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a diagram of its operating waveforms. 1...Word clock generation circuit, 2...Row-related address decoder, 3...Delay circuit, 4-4...Memory cell.

Claims (1)

[Scope of Claims] 1. A digit line, a plurality of word lines, a plurality of memory cells coupled to each of the plurality of word lines and the digit line, and a plurality of word lines that are connected to each other by an address signal. An MIS memory circuit in which a word line is driven by a timing signal, comprising: a selection means for supplying a timing signal to a designated word line; and a detection circuit for detecting a change in an address signal; and a timing signal generating means for forming a timing signal required to operate the MIS memory circuit in response to the output signal of the detection circuit, the word line being driven by a timing signal. MIS memory circuit. 2. The selection means receives the timing signal generated by the timing signal generation means and supplies the timing signal to the word line designated by the address signal. An MIS memory circuit in which a word line is driven by the timing signal described in item 1. 3. Each of the plurality of memory cells has information storage means, a first electrode coupled to the digit line, a second electrode coupled to the information storage means, and a gate electrode coupled to the corresponding word line.
MISFET, and the timing signal generating means is a memory cell coupled between a reference potential point and a predetermined potential point and coupled to a word line to which a timing signal is to be supplied, the memory cell being coupled to a word line to which a timing signal is to be supplied. The potential of the MISFET with respect to the reference potential is higher in absolute value than the potential of the digit line with respect to the reference potential during a period in which the first electrode of the MISFET serves as at least a drain and the second electrode of the MISFET serves as at least a source. An MIS memory circuit in which a word line is driven by a timing signal according to claim 2, wherein the MIS memory circuit forms a timing signal. 4. The timing signal generation means is characterized in that it has a timing signal generation circuit that generates a timing signal in response to the output signal of the detection circuit, and a bootstrap circuit that boosts the potential of the formed timing signal. An MIS memory circuit in which a word line is driven by the timing signal according to claim 3. 5. Claim 3, wherein the information storage means is constituted by a capacitive element.
An MIS memory circuit in which a word line is driven by the timing signal according to item 1 or 4.