JPS6130444B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic timepiece equipped with means for digitally adjusting the frequency.

[Conventional technology]

The configuration of a conventional electronic watch includes a constant frequency reference time signal generation circuit, a time unit signal generation circuit that divides the reference time signal to create time increments, a time measurement mechanism that maintains the time, and a time measurement unit that maintains the time. It was common to have a time adjustment mechanism to adjust settings. Here, the adjustment of speed has generally been achieved by finely adjusting the frequency of the reference signal or by digitally finely adjusting the frequency division ratio of the timekeeping unit signal generating circuit. Here, in the conventional digital frequency fine adjustment of the timekeeping unit signal, the relationship with the generation phase of the drive pulse was not taken into consideration when adjusting the frequency digitally.

[Problem that the invention seeks to solve]

Generally, when outputting drive pulses, 1
A current of about ~2mA flows. Therefore, in devices that use batteries as a power source, such as wristwatches, there is a possibility that the battery voltage will drop when the drive pulse is output, especially if it is cold and the residual current capacity is small, so frequency adjustment should be done at the same time. If you try to
There was a risk that the falling delay would increase, and that the amplitude of the power supply voltage would not be sufficient, leading to deviations from the operating range of the next stage, resulting in malfunction.

The object of the present invention is to provide an electronic timepiece that eliminates the above-mentioned drawbacks.

[Means for solving problems]

In order to achieve the above object, the electronic timepiece according to the present invention is equipped with means for making the time phase for digital frequency adjustment different from the time phase for generating drive pulses.

[Effect]

Description will be given below based on the drawings.

FIG. 1 is a block diagram of an electronic timepiece equipped with digital frequency adjustment means.

101 is a reference signal generation circuit, 102 is a clock unit signal production circuit, 103 is a clock device, 104 is a display device, 105 is a digital frequency adjustment circuit, 106
shows the entire basic clock blocks 101 to 104.

Generally, the digital frequency adjustment circuit 105 receives the output signal of the timekeeping unit signal generation circuit 103 and sends a correction control signal suitable for the required frequency correction amount to the timekeeping unit signal generation circuit 103. The correction control signal input to the time measurement unit signal generation circuit 103 changes the frequency division ratio of a part of the frequency divider of the time measurement device 103 to adjust the frequency.

〔Example〕

FIG. 2 shows an embodiment of the electronic timepiece according to the present invention, and FIGS. 3, 4, and 5 show the operation timing of each part.

In FIG. 2, 220 is a reference time signal generation circuit, 210 is a time measurement unit signal production circuit that divides the frequency of the reference time signal to produce time increments;
Drive pulses Q _A and Q _B are sent to the timekeeping mechanism that keeps the time. Furthermore, the above-mentioned time measurement unit signal generation circuit has 20
1 sends the output signal of the frequency divider to the digital frequency adjustment circuit 201, and outputs the correction control signal 206P _FC which is the output signal from the digital frequency adjustment circuit 201.
receive.

The 201 digital frequency adjustment circuit is configured as follows.

A phase setting circuit 202 receives the output signal of the frequency divider in the clock unit signal production circuit 201 and generates a weight pulse that determines the time phase of the correction control _206PFC and determines the amount of frequency adjustment. Frequency adjustment terminals J _C1 , J _C3 , J _C9 , J _C27 , J _F1 , J _F3 , J _F
9. A frequency adjustment setting circuit 211 that sets whether the frequency is increased or decreased or not adjusted by setting J _F27 to a high potential, a low potential, and an open state.

Timer circuit 2 that sets the frequency fine adjustment time
13. A synchronization signal generation circuit 214 sends out a signal for synchronizing the output signal of the frequency adjustment setting circuit 211 and the correction control signal _202PFC . Receives the phase setting circuit 202, frequency adjustment setting circuit 211, synchronization signal generation circuit 214, timer circuit 213, and frequency divider outputs in the clock unit signal generation circuit 210, and sends the correction control signal 206 to the clock unit signal generation circuit. A correction control signal generation circuit 218.

Below are figures 2, 3, 4, 5, and 6.
The operation will be explained based on FIG. 7, FIG. 8, and FIG.

In FIG. 3, φ ₆ to φ ₋₁ are the outputs of a frequency divider as a time unit signal generating circuit, and Q _A and Q _B represent drive pulses.

Phase setting circuit 202 output signals P ₁ , P ₃ , P ₉ , P ₂₇
is a weight pulse that determines the amount of frequency adjustment,
Each pulse is weighted 1, 3, 9, and 27, and the frequency is adjusted at the time phase when this pulse is output.

The frequency adjustment setting circuit 211 is connected to the frequency adjustment terminal J.
By setting _C1 to J _C27 and J _F1 to _{J F27} to a high potential, the frequency increases, by setting them to a low potential, the frequency decreases, and by leaving them open, the frequency does not increase or decrease. As _shown in _FIG .
The output signal 11 differs depending on the setting conditions of the frequency adjustment terminal. Frequency adjustment terminal J _C
1 to J _C27 are coarse adjustment terminals, and J _F1 to _{J F27} are fine adjustment terminals. Here, set the coarse adjustment terminal J _C27 to a high potential and the fine adjustment terminal J _F27 to a low potential, and set the remaining J _C1 and J _C
3. When the frequency adjustment terminals of J _C9 , J _F1 , J _F3 , and J _F9 are open, the output signal of the frequency adjustment setting circuit 211 is _{a 0} signal at 215, a φ ₀ signal at 216,
At 217, the potential becomes low.

The correction control signal generation circuit 218 includes signals 215, 216, and 217 of the frequency adjustment setting circuit 211.
AND circuit output 22 receives three types of output signals.
1, 222, 223, as shown in Figure 7, the selected wait pulse is output and the increase in frequency _{is 0.}
It can be seen that the decrease at the phase of φ is outputted at the phase of φ ₀ , respectively. Furthermore, the time measurement unit signal generation circuit 210
By combining with the frequency divider output of
Figure 4 is an enlarged timing chart showing the area around _B.

However, in Fig. 4, the frequency adjustment terminal J _C27 ,
The state in which _JF27 is both set to a high potential is shown. If we pay attention to _the drive pulse Q _B and the wait pulse P ₂₇ here, as shown in _{FIG .} There will be a phase difference of . By the way, 4.2MHz
A reference signal generation circuit that oscillates using an AT cut thickness shear oscillator as a reference oscillator, and a timer that divides the reference signal using a 1/5 dynamic frequency divider + 5/8 static variable frequency divider + static 1/2n frequency divider. According to this system example using a unit signal generation circuit, the above phase difference is approximately 970 μs. 204 is a data type flip-flop circuit for removing noise components from the weighted frequency adjustment signal and synchronizing it. Data type flip-flop circuit 2
Correction control signal 206P which is the output of 04
_{The FC} is synchronized by the output signal φ _12A of the simultaneous signal generation circuit 214, sent to the timekeeping unit signal generation circuit 210, and finally subjected to digital frequency adjustment by a 5/8 variable frequency divider.

FIG. 5 below shows an example in which digital frequency adjustment is performed by the 5/8 variable frequency divider 205. Output signal P _FC 2 of data type flip-flop circuit 204
When 06 is fixed at a low potential (that is, the frequency adjustment pulse is not output), the variable frequency divider 2
05 performs 5/8 frequency division. When the P _FC signal 206 is output, if the signal φ ₁₂ 207 is at a high potential, the output of the variable frequency divider 205 increases by one pulse and becomes equivalently divided by 6/8, and if the signal φ ₁₂ 207 On the other hand, if is at a low potential, the number of pulses decreases by one, equivalently
It is known that the frequency is divided into 4/8 and variable frequency division is performed.

From the above explanation, it can be seen that the time phase in which the drive pulse is generated and the time phase in which the digital frequency adjustment is performed are different.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
Since the time phase in which the drive pulse is generated and the time phase in which the digital frequency adjustment is performed are different, the residual current capacity of the battery is small and the battery voltage decreases as the drive pulse output occurs when the operating environment is low and the circuit elements As a result of the decrease in voltage amplification factor and decrease in operating speed, the pulse waveform becomes rounded and distorted as shown in Figure 8, and what should be a high potential level for subsequent operation is judged to be a low potential level, resulting in normal operation. Since the battery voltage is sufficiently restored without any failure, the effect on electronic watches that require high precision is great.

In the above embodiments, the drive pulse has been explained as being used implicitly to drive the motor, but it goes without saying that it is also effective in other cases, such as lighting a lamp.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an electronic watch, Figure 2 is a circuit diagram of an embodiment of the present invention, Figures 3, 4, and 5.
6, 7, and 8 are timing charts of an embodiment according to the present invention. 101... Reference signal generation circuit, 102... Time measurement unit signal production circuit, 103... Time measurement device, 104... Display device, 105... Digital frequency adjustment circuit, 106
...Basic clock block, 201...Digital frequency adjustment circuit, 202...Phase setting circuit, 205...5/8 variable frequency dividing circuit, 210...Time measurement unit signal generation circuit, 2
DESCRIPTION OF SYMBOLS 11... Frequency adjustment setting circuit, 213... Timer circuit, 214... Synchronization signal generation circuit, 218... Correction control signal production circuit, 220... Reference signal generation circuit.

Claims (1)

[Claims] 1. A time reference signal generation circuit that generates a reference signal of a constant frequency, a time measurement unit signal generation circuit that divides the frequency of the reference signal to create time measurement increments, a time measurement device that counts the time measurement unit signal to keep time, and In an electronic timepiece equipped with a frequency adjustment circuit that receives an output signal from a timekeeping unit signal generation circuit and sends a correction control signal to the timekeeping unit signal generation circuit, the frequency adjustment circuit includes a phase setting circuit, a frequency adjustment setting circuit. ,
The phase setting circuit receives the output signal of the time measurement unit signal production circuit, and produces a wait pulse signal having a phase different from that of the drive pulse that drives the time measurement device, and the phase setting circuit produces a wait pulse signal having a phase different from that of the drive pulse that drives the time measurement device. An electronic timepiece characterized in that a signal from a frequency adjustment setting circuit for setting the frequency adjustment amount is input to the correction control signal production circuit, and the frequency is adjusted using a correction control signal having a phase different from that of the drive pulse.