JPS6130849A - Demodulation circuit of 4-phase psk wave in time division multiplex signal - Google Patents

Abstract

PURPOSE:To demodulate a 4-phase DPSK wave by actuating a signal processing circuit given intermittently with a 4-phase DPSK wave on a time axis as a loop filter duing the existing period of an intermission signal and as a hold circuit during absence period. CONSTITUTION:The 1st switch 2 extracts separately a 4-phase DPSK wave (hereinafter 4-phase wave) subjected to time division multiplex with other signals from other signals. Respective demodulation signals are obtained from the burst 4-phase wave by the 1st phase detector 3 and the 2nd phase detector 4. Each demodulation signal is fed to the 1st signal processing circuit 9 to generate an error signal in the state where the phase change corresponding to a modulation signal of the 4-phase wave is cancelled. The 2nd signal processing circuit 13 acts as a loop filter to an error signal of the circuit 9 when the 4-phase wave is fed to the phase detectors 3, 4, and acts like a hold circuit of the error signal of the circuit 9 during the period other than the said period. An output of the circuit 13 controls a voltage controlled oscillator 6, its output is fed respectively to the phase detectors 3, 4 to demodulate the 4-phase wave.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is a circuit for demodulating four-phase DPSK waves in a time division multiplexed signal, and in particular includes a carrier regeneration means for performing signal processing in the baseband. 4-phase D in the time division multiplexed signal
This relates to a PSK wave demodulation circuit.

(Conventional technology) Wireless transmission systems using PSK including 4-phase DPSK are as follows:
It is known as a transmission method that is advantageous in transmitting a large amount of information within a certain bandwidth because it can transmit a large amount of information per unit time compared to wireless transmission methods that use frequency modulation. For example, when transmitting an audio signal in satellite broadcasting, a digital signal formed by converting the audio signal into PCM is required to be transmitted as a 4-phase DPSK wave.
It is also well known that 4-phase DPSK is frequently used for wireless transmission of various information.

As a means of demodulating the above-mentioned four-phase DPSK waves, a synchronous detection method that exhibits excellent characteristics in various aspects such as transmission efficiency, noise resistance, and interference resistance is usually adopted. Although a carrier wave is required for synchronous detection, the carrier wave is suppressed in PSK waves, so
In order to perform synchronous detection of PSK waves, a carrier wave regeneration circuit for regenerating a carrier wave from the PSK wave is required.

The above-mentioned carrier wave regeneration circuit is an important circuit that greatly affects the demodulation characteristics of the PSK wave, and conventional carrier wave regeneration circuits have been used for example in multiplication systems that belong to methods that perform signal processing in the carrier band and regenerate the carrier wave. , a carrier wave regeneration circuit configured according to a remodulation method, an inverse modulation method, etc., a costas loop method, which belongs to a method that performs signal processing in a base node and regenerates a carrier wave, and a modified method of the costas loop method. Carrier wave recovery circuits configured according to various formats have been proposed, such as carrier wave recovery circuits configured according to Because it is cheaper and signal processing is performed in a lower frequency band, multipliers are mainly used and signal processing is performed in a lower frequency baseband, such as the Costas loop method or a variant of the Costas loop method. Carrier wave regeneration circuits configured according to the above are increasingly being used.

A phase-locked loop is the basic structure of a carrier regeneration circuit configured according to the Costas loop method or a modified method of the Costas loop method in which signal processing of 4-phase DPSK waves is performed at a low frequency baseband. Therefore, it is necessary that each circuit making up the phase-locked loop has good operational stability.

The present applicant company previously proposed in Japanese Patent Application No. 59-46880 that it uses a double balanced phase detector that operates well even in high frequency bands instead of an analog multiplier, and that it has an analog multiplier with good linearity. We have proposed a carrier wave regeneration circuit that operates with high performance equivalent to that of a carrier wave recovery circuit configured using .

(Problem that J?! Ming tries to solve) By the way, when the 4-phase DPSK wave and other signals are time-division multiplexed, the 4-phase DPSK wave in the time-division multiplexed signal is Conventional carrier wave regeneration circuits, which are configured to regenerate carrier waves for synchronous detection using four-phase DPSK waves that exist continuously on the time axis, It cannot be used as a carrier regeneration circuit when demodulating the four-phase DPSK wave in a division multiplexed signal, so time division multiplexing, which includes a carrier regeneration circuit that can operate with high stability, cannot be used. The appearance of a demodulation circuit for the 4-phase DPSK wave in the signal has been long awaited.

(Means for Solving the Problems) The present invention provides four-phase DPSK modulated waves in a time division multiplexed signal including a carrier wave regeneration circuit for regenerating a carrier wave used in synchronous detection of a four-phase DPSK modulated wave. A demodulation circuit for phase DPSK waves, which includes a first switch for separating and extracting a four-phase DPSK wave that is time-division multiplexed with other signals from other signals; The burst-like 4-phase DPSK wave thus obtained is supplied to the first phase detector and the second phase detector, and the first phase detector described above is supplied to the first phase detector and the second phase detector. A means for obtaining respective demodulated signals from the second phase detector and respective demodulated signals from the first and second phase detectors described above are supplied as input signals, thereby generating a modulated signal in the four-phase DPSK wave. a first signal processing circuit configured to generate an error signal in which a phase change corresponding to It is configured to include a switch, and the above-mentioned first. 4 for the second phase detector
During the period when the phase DPSK wave is supplied, it operates as a loop filter for the error signal generated in the first signal processing circuit described above, and during the period other than the period described above, the first signal processing circuit described above operates. a second signal processing circuit that operates as a hold circuit for the error signal supplied from the second signal processing circuit, a voltage controlled oscillator to which the output signal of the second signal processing circuit is supplied as an error voltage, and the voltage controlled oscillator described above. (means for giving the own call as a carrier wave for synchronous detection to the first phase detector, and the output signal from the voltage controlled oscillator described above is passed through a 90 degree phase shift circuit to the second phase detector described above. The present invention provides a demodulation circuit for a four-phase DPSK wave in a time-division multiplexed signal, comprising means for providing a carrier wave for synchronous detection to a time division multiplexed signal.

(Embodiment) Hereinafter, the specific contents of the demodulation circuit for four-phase DPSK waves in a time division multiplexed signal of the present invention will be explained in detail with reference to the accompanying drawings of FIGS. 1 to 4.

FIG. 1 is a block diagram for explaining an embodiment of a demodulation circuit for four-phase DPSK waves in a time-division multiplexed signal according to the present invention, and FIG. Phase DP
FIG. 3 is a block diagram for explaining the principle of baseband signal processing performed in the SK wave demodulation circuit; FIG. The figure shows four-phase DP in the time division multiplexed signal of the present invention.
FIG. 3 is an explanatory diagram of the operation of the SK wave demodulation circuit.

Now, before going into the explanation of the demodulation circuit for 4-phase DPSK waves in a time-division multiplexed signal of the present invention, we will make it easier to understand the contents of the demodulation circuit for 4-phase DPSK waves in a time-division multiplexed signal of the present invention. For this purpose, an example of how 4-phase DPSK is used will first be described using Japanese satellite broadcasting as an example.

In the case of Japanese satellite broadcasting, binary data based on play codes is processed in two series, and the data change periods are 0 radian for (0,0) and 0 radian for (0,1).
π/2 radians for and π for (1,,1)
For radians (i, o), it is determined as 3π/2 radians.

The four-phase DPSK wave that is generated according to the phase change side as described above has its carrier wave suppressed, but the phase change in the four-phase DPSK wave can be suppressed by some method. If you can cancel it, 4
It is possible to recover a carrier wave corresponding to a carrier wave before modulation from a carrier wave suppressed in a phase DPSK wave.1 In the carrier wave recovery means in the demodulation circuit for four-phase DPSK waves in a time division multiplexed signal of the present invention, By multiplying the baseband signal by 4, the π/2 phase change in the 4-phase DPSK wave becomes a 2π phase change, and the π phase change in the 4-phase DPSK wave becomes 4
Multiplication results in a phase change of (2π×2), and further, 4
Focusing on the point that the phase change of 3π/2 in the phase DPSK wave becomes a phase change of (2π × 3) by multiplying by 4, which can cancel out the phase change in the 4-phase SK wave. The carrier wave is synchronously reproduced from the four-phase DPSK wave.

In the demodulation circuit for the four-phase DPSK wave in the time-division multiplexed signal of the present invention shown in the block diagram of FIG. This is performed in the first signal processing circuit 9 labeled with .

Furthermore, in the demodulation circuit for the 4-phase DPSK waves in the time-division multiplexed signal of the present invention, the 4-phase DPSK waves in the time-division multiplexed signal are used as the target signal for demodulation. As a countermeasure to the intermittent loss of the error signal, which is a problem when 4-phase DPSK is used,
A second method configured by applying a means of holding an error signal immediately before a period in which a wave is missing and using it as an error signal during a period in which a four-phase DPSK wave is in a state in which a wave is missing. A signal processing circuit 13 is used.

That is, as the second signal processing circuit 13, a 4-phase DPS
The four-phase circuit is designed so that it operates as a loop filter during the period when the K wave is present, and as a hold circuit during the period when the wave is missing in the four-phase blade S. The period during which the DPSK wave exists and the 4-phase DP
By configuring the system so that it can be switched between two operating modes depending on the period during which no SK waves are present,
Even if the error signal is missing during the period when the phase-locked SK wave is missing, the phase-locked loop is basically allowed to operate while the loop gain is reduced.

In FIG. 1, 1 is an input terminal, 2 is a switch whose opening/closing is controlled by a control signal Sc, 3 and 4 are phase detectors, and 5
is a π/2 phase shifter, 6 is a voltage controlled oscillator, 7 and 8 are low-pass filters for removing carrier wave components, 9 is a first signal processing circuit, and 10 is a signal in the first signal processing circuit 9. Input terminal 11 is Q in the first signal processing circuit 9
Signal input terminal, 12 is an output terminal in the first signal processing circuit 9, 13 is a second signal processing circuit, 14 is a second signal processing port, input terminal in path 13, 15 is a second signal processing circuit 13 is an output terminal, 16 is an output terminal for the engineering signal Si, 17 is an output terminal for the Q signal Sq, 18, 19,
23 and 24 are double balanced phase detectors, 22 are inverting amplifiers with a gain of 1, 20 and 21 are subtraction circuits, 25 and 26 are waveform shaping circuits, 27 is an exclusive OR circuit, 28 is a resistor, 29
is a switch 30 whose opening/closing is controlled by a control signal Sc;
31 is a capacitor, 31 is an amplifier, and 32 is an input terminal for the control signal Sc.

In addition, in Fig. 2, 33.34 are input terminals, 35
, 36° and 37 are analog multipliers, and 38 is an output terminal.

At the input terminal 1 of the demodulation circuit for the 4-phase DPSK wave in the time-division multiplexed signal of FIG. 1, the 4-phase DPSK wave and other signals as shown in (a) of FIG. When the signal Si is supplied and the switch 2 is controlled to open and close by the control signal Sc as shown in FIG. 4-phase DP in a time division multiplexed signal as shown in FIG. 3(c)
The SK wave SO is separated and extracted and supplied.

In the phase detector 3 described above, synchronous detection is performed using the recovered carrier wave C1 outputted from the voltage controlled oscillator 6, and the I signal SN is demodulated via the low-pass filter 7 and sent to the output terminal 16.

Furthermore, in the phase detector 4, synchronous detection is performed using the recovered carrier C2, which is obtained by phase-shifting the recovered carrier C1 outputted from the voltage controlled oscillator 6 by the π/2 phase shifter, and the Q signal Sq is outputted via the low-pass filter 8. It is demodulated and sent to the output terminal 17.

The above-mentioned I signal SN is input to the first input terminal X of the double balanced phase detector 18 in the first signal processing circuit 9, the second input terminal Y of the double balanced phase detector @23, and the second input terminal Y of the double balanced phase detector @23. The signal is supplied to the first input terminal X and the second input terminal Y of the double-balanced phase detector 24 .

Furthermore, the Q signal Sq described above is transmitted to the second input terminal Y of the double balanced phase detector 18 in the first signal processing circuit 9 and the first input terminal X of the double balanced phase detector 19. It is supplied to the first input terminal X of the double-balanced phase detector 23 via the second input terminal Y and the inverting amplifier 22 with a gain of 1.

Therefore, each of the double balanced phase detectors 18, 19 .
23.24, each of the first . A multiplication operation is performed on the input signals supplied to the second input terminals X and Y, and multiplied signals are respectively output.

That is, the multiplication signal output from the double-balanced phase detector 18 is supplied to the first subtraction circuit 20 as a minuend signal, and the multiplication signal output from the double-balanced phase detector 23 is By being given as a subtraction signal to the first subtraction circuit 20 described above, the first subtraction circuit 20 outputs a first subtraction signal.

A first square signal is output from the double balanced phase detector 19 and supplied to the second subtraction circuit 21 as a minuend signal, and a multiplication signal output from the double balanced phase detector 24 is given to the second subtraction circuit 21 as a subtraction signal, so that the second subtraction circuit 21 outputs the second subtraction signal.
A subtraction signal is output.

The above-mentioned first subtraction signal is waveform-shaped by the waveform shaping circuit 25 and then supplied to the exclusive OR circuit 27, and the above-mentioned second subtraction signal is waveform-shaped by the waveform shaping circuit 26 and then supplied to the exclusive OR circuit 27. The error signal is supplied to the exclusive OR circuit 27, and the error signal is output from the exclusive OR circuit 27.

The outline of the operation of the first signal processing circuit 9 indicated by block 9 in FIG.
The operation of the first signal processing circuit 9 will be explained in more detail with reference to FIGS.

Now, the phase change in the regenerative transport output from the voltage controlled oscillator 6 is 0. π/2. π, 3π/2) and
The output of the low-pass filter is (Δ1.-A2c
os φ)/2 is obtained, and (AI·A25in φ)/2 is obtained as the output of the low-pass filter 8.

In the following explanation, for the sake of simplicity, the amplitude A
The description is made by omitting the display of I and A2 and focusing only on the phase change.

The double balanced phase detector 18 in FIG. 1 corresponds in principle to the analog multiplier 35 in FIG. 2, and the double balanced phase detector 19 in FIG. Since it corresponds to the analog multiplier 36 in FIG. 2, 5in2φ is obtained as the output of the analog multiplier 35 in FIG.
-cos2φ is obtained as the output.

The exclusive OR circuit 27 in FIG. 1 performs the same operation as the analog multiplier 37 in FIG. 2, but the output of the analog multiplier 37 is -5in4φ
Therefore, it can be obtained as demodulated output (A1-A2 c
The phase changes in osφ)/2 and (AI-A2 sin φ)/2 are multiplied by four. In addition, general analog multipliers have perfect linearity,
Although the multiplication and squaring operations described above can be performed almost ideally, it is difficult to use them at frequencies above 1 MHz at the current technological level in the operating frequency range, so other elements with good high frequency characteristics may be used instead. The need arises. In the embodiment circuit of the present invention, the analog multiplier 3
5, by using a double-balanced phase detector with good high frequency characteristics, an exclusive OR circuit, etc., so that the signal processing operation of the embodiment circuit shown in the first figure is the same as the signal processing in the circuit shown in the second figure. I'm trying to make it equivalent to the behavior.

That is, 4 in the time division multiplexed signal of the present invention shown in FIG.
In the phase DPSK wave demodulation circuit, the operating characteristics of the phase detector 3 can be shown in FIG. 4 (a), and the operating characteristics of the 1-phase detector 4 can be shown in FIG. 4 (b). I can do it,
Furthermore, the operating characteristics of the double balanced phase detector 18 are shown in (c) of FIG. 4, and the operating characteristics of the double balanced phase detector 23 are shown in (d) of FIG. The subtraction operation by the first subtraction circuit 2o is as shown in FIG. 4(a).

On the other hand, since the double-balanced phase detectors 19 and 24 operate squarely in principle, the double-balanced phase detector 19
The operating characteristics of the double-balanced phase detector 24 are shown in (f) in FIG. 4, and the operating characteristics of the double-balanced phase detector 24 are shown in (g) in FIG. The operation is as shown in (h) in Figure m14.

The operating characteristics of the exclusive OR circuit 27 are shown in FIG.
i).

Now, the error signal output from the first signal processing circuit 9 described above is supplied to the second signal processing circuit 13. Second
The switch 29 (second switch) in the signal processing circuit 13 switches the switch 2 (second switch) described above in response to the control signal Sc.
The opening/closing operation is performed in synchronization with the first switch).
Switch 29 is turned on during a period when a 4-phase DPSK wave exists, and switch 29 is turned on during a period when a 4-phase DPSK wave is not present.
9 is turned off.

The second period in which the switch 29 is in the on state, that is, the period in which the four-phase DPSK wave is present.
The signal processing circuit 13 forms a loop filter with the resistor 28 and the capacitor 30, and the second signal processing circuit 13 in this state
The signal processing circuit 13 converts the error signal supplied from the first signal processing circuit 9 into an error voltage by the action of a loop filter, thereby controlling the oscillation frequency of the voltage controlled oscillator 6, that is, the reproduced carrier frequency. to be done.

The period during which the switch 29 is turned off.

That is, the second signal processing circuit 13 in the period when the 4-phase DPSK wave is not present receives the error signal in the period when the 4-phase DPSK wave is present, and the capacitor 30 converts the error signal in the period in which the 4-phase DPSK wave is not present. The voltage is maintained at a voltage inside the voltage control oscillator 6 as a control voltage.

As is clear from the above explanation, in the demodulation circuit for the 4-phase DP5 wave in the time division multiplexed signal of the present invention shown in FIG.
The phase change amount φ of the wave is 4 in the first signal processing circuit 9.
Since only the phase error generated in the phase-locked loop is converted into an error voltage and is used to control the voltage controlled oscillator, the recovered carrier wave becomes stable and the phase detector 3.4 becomes stable. It will operate correctly, and the I signal and Q signal as demodulated output of the 4-phase DPSK wave will be sent to the output terminals 16 and 17. Although the first signal processing circuit uses the exclusive OR circuit 27, other circuit configurations such as a double balanced phase detector or a phase detector may be used instead of the exclusive OR circuit. Of course, a circuit configuration configured using the above may also be adopted.

(Effects) As is clear from the detailed explanation above, the demodulation circuit for the four-phase DPSK wave in the time division multiplexed signal of the present invention has the following features:
A demodulation circuit for a 4-phase DPSK wave in a time division multiplexed signal, which includes a carrier wave regeneration circuit for regenerating a carrier wave used in synchronous detection of a 4-phase DPSK modulated wave, a first switch for separating and extracting the time-division multiplexed four-phase DPSK wave from other signals;
The burst-like four-phase DPSK wave separated and extracted by the first switch described above is supplied to the first phase detector and the second phase detector. means for obtaining respective demodulated signals from the second phase detector; The configuration is configured to generate an error signal in which the phase change corresponding to the modulation signal in the 4-phase DPSK wave is canceled by supplying each demodulated signal from the second phase detector as an input signal. and a second switch that performs a switching operation in synchronization with the switching operation of the first switch,
The first point mentioned above. 4-phase DPSK for the second phase detector
During the period when the wave is supplied, it operates as a loop filter for the error signal generated by the first signal processing circuit described above, and during periods other than the period described above, the signal is supplied from the first signal processing circuit described above. a second signal processing circuit that operates as a hold circuit for the error signal that has been previously used; a voltage controlled oscillator to which the output signal of the second signal processing circuit is supplied as an error voltage; Means for providing the output signal to the first phase detector as a carrier wave for synchronous detection; and means for providing the output signal from the voltage controlled oscillator described above to the second phase detector for synchronous detection via a 90 degree phase shift circuit. 1. In the demodulation circuit for a 4-phase DPSK wave in a time-division multiplexed signal according to the present invention, the first The second signal processing circuit 13, which is supplied with the signal intermittently generated by the signal destination circuit, operates as a loop filter during the period when the four-phase DPSK wave is present. During the period when the 4-phase DPSK wave is present, it operates as a hold circuit.
It is configured to be able to switch between two types of operation mode depending on the period in which the phase DPSK wave is not present, and
Even if the error signal is missing during the period when the phase DPSK wave is missing,
Basically, it is designed to be able to perform phase-locked loop operation while limiting the loop gain to a decrease.1 The demodulation circuit for the 4-phase DPSK wave in the time division multiplexed signal of the present invention is capable of performing the 1 time division multiplexed signal. According to the present invention, the above-mentioned conventional problems can be solved satisfactorily.

In addition, since the first signal processing circuit used as a carrier wave regeneration circuit in implementing the present invention performs signal processing in the baseband, the frequency handled is lower than that in the case where signal processing is performed in the carrier band. This makes it easy to increase the stability of operation, making it ideal for integrated circuits, and because it uses a double-balanced phase detector instead of an analog multiplier. , there are no problems when using it in high frequency bands, and furthermore, double-balanced phase detectors have poor linearity compared to original analog multipliers, but double-balanced phase detectors By using a balanced configuration using two phase detectors each, the asymmetry of the operating waveform was significantly improved, and as a result, an analog multiplier with good linearity was used. In addition to achieving high-performance operation equivalent to that in the conventional case, the problem of DC drift caused by temperature changes in double-balanced phase detectors is greatly improved by the cancellation effect of subtraction. In this respect as well, the present invention has the advantage that an integrated circuit capable of highly stable operation can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a demodulation circuit for four-phase SK waves in a time-division multiplexed signal according to the present invention, and FIG. 2 is a block diagram of an embodiment of a demodulation circuit for four-phase DPSK waves in a time-division multiplexed signal according to the present invention. 3 is a block diagram for explaining the principle of baseband signal processing carried out in the present invention. FIG. FIG. 2 is an explanatory diagram of the operation of a demodulation circuit for a four-phase DPSK wave in a division multiplexed signal. 1... Input terminal for 4-phase SK wave, 2, 29... Switch, 3.4... Phase detector for synchronous detection, 5...
90 degree phase shifter, 6... voltage controlled oscillator, 7, 8... low pass filter, 9... first signal processing circuit, 1g,
19,23.24...double balanced phase detector, 13.
...Second signal processing circuit, 20.21...Subtraction circuit,
25.26... Waveform shaping circuit, 35-37... Analog multiplier Φ approximately -01'-.

Claims (1)

[Claims] A demodulation circuit for 4-phase DPSK waves in a time division multiplexed signal, which includes a carrier wave regeneration circuit for regenerating a carrier wave used in synchronous detection of 1- and 4-phase DPSK modulated waves. 4-phase DPS that is time-division multiplexed with other signals
A first switch for separating and extracting the K wave from other signals, and a first phase detector and a second phase detector to detect the burst-like four-phase DPSK wave separated and extracted by the first switch. and means for obtaining respective demodulated signals from the first and second phase detectors, and means for supplying the respective demodulated signals from the first and second phase detectors as input signals. a first signal processing circuit configured to generate an error signal in which a phase change corresponding to a modulated signal in a four-phase DPSK wave is canceled by switching the first switch; It is configured to include a second switch that performs a switching operation in synchronization with the operation, and provides a four-phase DP signal to the first and second phase detectors.
During the period when the SK wave is supplied, it operates as a loop filter for the error signal generated by the first signal processing circuit described above, and during periods other than the period described above, it operates as a loop filter for the error signal generated by the first signal processing circuit described above. a second signal processing circuit that operates as a hold circuit for the supplied error signal;
a voltage controlled oscillator to which the output signal of the second signal processing circuit is supplied as an error voltage; means for providing the output signal from the voltage controlled oscillator to the first phase detector as a carrier wave for synchronous detection; 4-phase DPSK wave in a time division multiplexed signal, comprising means for supplying the output signal from the voltage controlled oscillator to the above-mentioned second phase detector as a carrier wave for synchronous detection via a 90 degree phase shift circuit. The demodulation circuit 2 includes a first double-balanced phase detector as a first signal processing circuit, the demodulated signal from the first phase detector being supplied to a first input terminal. means for supplying the demodulated signal from the second phase detector to a second input terminal of the second phase detector to obtain a first multiplied signal from the first double-balanced phase detector; The above-mentioned phase detector is connected to a second input terminal of a second double-balanced phase detector, in which a signal obtained by inverting the phase of the demodulated signal from the phase detector is supplied to the first input terminal. means for supplying the demodulated signal from the first phase detector to obtain a second multiplied signal from the second double-balanced phase detector; means for supplying the signal to the first subtraction circuit to obtain the first subtraction signal, and a demodulated signal from the second phase detector described above is supplied to the first input terminal and the second input terminal. means for obtaining a first square signal from a third double-balanced phase detector configured as above, and a demodulated signal from the first phase detector described above is connected to a first input terminal and a second input terminal. means for obtaining a second squared signal from a fourth double-balanced phase detector configured to be supplied to a terminal; a means for supplying the signal to a second subtraction circuit to obtain a second subtraction signal; and a means for shaping the waveforms of the first subtraction signal and the second subtraction signal, respectively, and then supplying the signal to an exclusive OR circuit. demodulation of a four-phase DPSK wave in a time division multiplexed signal according to claim 1, wherein Circuit 3 is an amplifier to which the error signal is supplied via a resistor, a second switch, and a capacitor, as a second signal processing circuit to which the error signal output from the first signal processing circuit is supplied as an input signal. During the zero period of the four-phase DPSK wave, it holds the error signal just before the four-phase DPSK wave becomes zero, and functions as a loop filter during the period when the four-phase DPSK wave is occurring. Claim 1 consisting of a device configured to
4-phase DPSK wave demodulation circuit in the time division multiplexed signal described in 2.