JPS6136590U - timer display device - Google Patents

timer display device

Info

Publication number
JPS6136590U
JPS6136590U JP12142984U JP12142984U JPS6136590U JP S6136590 U JPS6136590 U JP S6136590U JP 12142984 U JP12142984 U JP 12142984U JP 12142984 U JP12142984 U JP 12142984U JP S6136590 U JPS6136590 U JP S6136590U
Authority
JP
Japan
Prior art keywords
reservation
display
time
error
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12142984U
Other languages
Japanese (ja)
Inventor
一義 高石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12142984U priority Critical patent/JPS6136590U/en
Publication of JPS6136590U publication Critical patent/JPS6136590U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係るタイマー表示装置の表
示態様を示す平面図、第2図は同上装置の回路構成の一
例を概略的に示すブロック図、第′ 3図は第2のメモ
リ・制御部を詳細に示すブロック図、第4図は同じく第
2図の表示制御部を詳細に示すブロック図、第5図は第
4図の表示動作のタイミングを示すタイムチャート、第
6図は本考案の他の表示態様を説明するための説明図、
第7図は従来のタイマー表示装置の表示面の一例を示す
説明図である。 1・・・入力部、2・・・処理回路、3・・・メモリ・
制御部、4・・・時計用クロツク発生部、5・・・表示
制御部、6・・・ビデオテープレコーダ、7,8・・・
表示駆動部、9・・・表示部、10〜13・・・セグメ
ント表示器、32〜35・・・メモリ、36・・・プロ
グラム制御回路、51・・・表示信号発生回路、52〜
55・・・表”示信号切換回路、56ト・・桁信号発生
回路、57・・・エラー表示信号発生器、58・・・開
閉スイッチ回路、59・・・切換スイッチ回路。
FIG. 1 is a plan view showing a display mode of a timer display device according to an embodiment of the present invention, FIG. 2 is a block diagram schematically showing an example of the circuit configuration of the same device, and FIG. FIG. 4 is a block diagram showing the memory/control unit in detail; FIG. 4 is a block diagram showing the display control unit shown in FIG. 2 in detail; FIG. 5 is a time chart showing the timing of the display operation in FIG. 4; FIG. are explanatory diagrams for explaining other display modes of the present invention,
FIG. 7 is an explanatory diagram showing an example of a display surface of a conventional timer display device. 1...Input section, 2...Processing circuit, 3...Memory
Control unit, 4...Clock generation unit, 5...Display control unit, 6...Video tape recorder, 7, 8...
Display drive unit, 9...Display unit, 10-13...Segment display device, 32-35...Memory, 36...Program control circuit, 51...Display signal generation circuit, 52-
55... Table display signal switching circuit, 56... Digit signal generation circuit, 57... Error display signal generator, 58... Open/close switch circuit, 59... Changeover switch circuit.

Claims (1)

【実用新案登録請求の範囲】 タイマー可能な一定期間内に設定される予約時間を、前
記設定のためのプログラムの数に対応して複数有し、こ
れらのプログラムをナンバーで区別するようにした予約
手段と、 この予約手段で設定した予約時間を各時間桁ごとに表示
するセグメント表示器から成る表示手段と、 前記予約手段に設定された予約時間のデータ内容をチェ
ックしてエラーの有無を判別し、エラーを含んだ予約時
間を設定したプログラムのナンバーが前記表示手段の表
示する時間桁に対応するように該当する所定のセグメン
ト表示器をエラー表示するエラー表示手段とを具備した
ことを特徴とするタイマー表示装置。
[Claims for Utility Model Registration] A reservation that has a plurality of reservation times set within a certain time period that can be timed, corresponding to the number of programs for the setting, and these programs are distinguished by numbers. a display means comprising a segment display for displaying the reservation time set by the reservation means for each time digit; and a display means comprising a segment display for displaying the reservation time set by the reservation means for each time digit, and checking the data content of the reservation time set by the reservation means to determine the presence or absence of an error. and an error display means for displaying an error on a corresponding predetermined segment display so that the number of the program in which the reservation time containing the error is set corresponds to the time digit displayed by the display means. Timer display device.
JP12142984U 1984-08-09 1984-08-09 timer display device Pending JPS6136590U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12142984U JPS6136590U (en) 1984-08-09 1984-08-09 timer display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12142984U JPS6136590U (en) 1984-08-09 1984-08-09 timer display device

Publications (1)

Publication Number Publication Date
JPS6136590U true JPS6136590U (en) 1986-03-06

Family

ID=30680214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12142984U Pending JPS6136590U (en) 1984-08-09 1984-08-09 timer display device

Country Status (1)

Country Link
JP (1) JPS6136590U (en)

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