JPS6140077U - Television receiver AGC device - Google Patents
Television receiver AGC deviceInfo
- Publication number
- JPS6140077U JPS6140077U JP12450484U JP12450484U JPS6140077U JP S6140077 U JPS6140077 U JP S6140077U JP 12450484 U JP12450484 U JP 12450484U JP 12450484 U JP12450484 U JP 12450484U JP S6140077 U JPS6140077 U JP S6140077U
- Authority
- JP
- Japan
- Prior art keywords
- television receiver
- agc device
- agc
- receiver agc
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Receiver Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【図面の簡単な説明】
第1図は従来のAGC装置を説明する回路のブロック図
、第2図はこの考案の一実施例のAGC装置を説明する
回路のブロック図である。
1・・・フロントエンド、2・・−SAWフィルタ、3
・・・映像中間周波数増幅器、−4・・・映像検波部、
5・・・映像増幅部、6・・・PLLシンセサイザ、7
・・・ROM,訃・・AGC部、80・・・雑音除去部
、81・・・AGC検波部、82・・・AGC増幅部、
83・・・RF・AGC部、9・・・CPU,IQ・・
・D/Aコンバータ。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a circuit illustrating a conventional AGC device, and FIG. 2 is a block diagram of a circuit illustrating an AGC device according to an embodiment of the present invention. 1...Front end, 2...-SAW filter, 3
...Video intermediate frequency amplifier, -4...Video detection section,
5... Video amplification section, 6... PLL synthesizer, 7
...ROM, ...AGC section, 80...Noise removal section, 81...AGC detection section, 82...AGC amplification section,
83...RF/AGC section, 9...CPU, IQ...
・D/A converter.
Claims (1)
と、AGC回路よりの電圧とをフロントエンドに印加し
て、ゲインコントロールを行うテレビジョン受像器にお
いて、上記PLLシンセサイザを作動させるROMに収
納された上記AGC回路の各チャンネルごとの最適立上
り時点に対応するデーによって、上記ゲインコントロー
ルを作動させることを特徴とするテレビジョン受像器の
AGC・装置。In a television receiver that performs gain control by applying a tuning voltage for each channel from a PLL synthesizer and a voltage from an AGC circuit to the front end, the AGC circuit stored in a ROM operates the PLL synthesizer. An AGC/device for a television receiver, characterized in that the gain control is operated according to a date corresponding to an optimum rise time for each channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12450484U JPS6140077U (en) | 1984-08-15 | 1984-08-15 | Television receiver AGC device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12450484U JPS6140077U (en) | 1984-08-15 | 1984-08-15 | Television receiver AGC device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6140077U true JPS6140077U (en) | 1986-03-13 |
Family
ID=30683231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12450484U Pending JPS6140077U (en) | 1984-08-15 | 1984-08-15 | Television receiver AGC device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6140077U (en) |
-
1984
- 1984-08-15 JP JP12450484U patent/JPS6140077U/en active Pending
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