JPS614202U - Phase difference control device - Google Patents
Phase difference control deviceInfo
- Publication number
- JPS614202U JPS614202U JP8152085U JP8152085U JPS614202U JP S614202 U JPS614202 U JP S614202U JP 8152085 U JP8152085 U JP 8152085U JP 8152085 U JP8152085 U JP 8152085U JP S614202 U JPS614202 U JP S614202U
- Authority
- JP
- Japan
- Prior art keywords
- phase difference
- control device
- difference control
- circuit
- logic gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Feedback Control In General (AREA)
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による位相差制御装置の実施例を示す回
路図、第２図および第３図は本考案のによる位相差制御
装置の他の２つの実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the phase difference control device according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing two other embodiments of the phase difference control device according to the present invention.
Claims (5)
１対のデイジタル位相差保持回路に入力論理ゲートを介
してクロック信号発生器を結合し、これらデイジタル位
相差保持回路の分周比の等しい箇所からの出力即ち第１
出力を位相差制御装置自体の１対の出力端子にそれぞれ
結合し、一方のデイジタル位相差保持回路の前記第１出
力および前記入力論理ゲートの間に位相差制御回路を備
え、前記＆相差制御回路にはインパルス発生回路、制御
論理ゲートおよび手動または遠隔操作スイッチを設け、
手動または遠隔操作スイッチにより制御論理ゲートを制
御して制御論理インパルス発生回路から入力論理ゲート
へのクロック停止信号の供給を制御し、これに対応して
クロツク信号発生器からいずれかのデイジタル位相差保
持回路へのクロック信号の供給を停止するこ−とにより
前記１対の出力端子に生ずる出力信号の位相差を制御す
るよう構成したことを特徴とする位相差制御装置。(1) A clock signal generator is coupled via an input logic gate to a pair of digital phase difference holding circuits having a frequency division function and forming a phase difference holding section, and the frequency division ratio of these digital phase difference holding circuits is Outputs from equal locations, i.e. the first
outputs are respectively coupled to a pair of output terminals of the phase difference control device itself, and a phase difference control circuit is provided between the first output of one digital phase difference holding circuit and the input logic gate, and the &phase difference control circuit is equipped with an impulse generating circuit, a control logic gate and a manual or remote control switch,
The control logic gate is controlled by a manual or remote control switch to control the supply of the clock stop signal from the control logic impulse generator circuit to the input logic gate, and correspondingly, the clock signal generator outputs one of the digital phase difference hold signals. A phase difference control device, characterized in that the phase difference control device is configured to control the phase difference between the output signals generated at the pair of output terminals by stopping the supply of a clock signal to the circuit.
差制御装置において、インパルス発生回路から供給する
クロツク停止信号の単位時間当たりの供給回数または供
給持続時間を選択するようにより前記位相差を種々の制
御速度で調整できるよう構成したことを特徴とする位相
差制御装置。(2) Utility Model Registration In the phase difference control device according to claim 1, the phase difference is controlled by selecting the number of times or duration of supply of the clock stop signal supplied from the impulse generating circuit per unit time. A phase difference control device characterized in that it is configured to be adjustable at various control speeds.
御装置において、インパルス発生回路の入力端子を選択
スインチを介し前記一方のディジタル位相差保持回路に
おける前記第１出力の他に互いに分周比の異なる（ｍ−
１）個の箇所からの出力に結合できるようにし、合計ｍ
種類の位相差制御速度を選択できるよう構成したことを
特徴とする位相差制御装置。(3) Utility model registration In the phase difference control device according to claim 2, the input terminals of the impulse generation circuit are separated from each other in addition to the first output of the one digital phase difference holding circuit through a selection switch. Different circumferential ratios (m-
1) It is possible to combine the outputs from several locations, and the total m
A phase difference control device characterized in that it is configured so that different types of phase difference control speeds can be selected.
御装置において、前記インパルス発生回路に対し互いに
クロツク停止信号送出時間の異なる（ｎ−１’）個のイ
ンパルス発生回路を選択スイツチを介し並列に付加接続
し、合計ｎ種類の位相差制御速度を選択できるよう構成
したことを特徴とする位相差制御装置。(4) Utility Model Registration In the phase difference control device according to claim 2, a selection switch is provided to select (n-1') impulse generating circuits having different clock stop signal sending times for the impulse generating circuit. What is claimed is: 1. A phase difference control device characterized in that the phase difference control device is additionally connected in parallel through the phase difference control device so as to be able to select a total of n types of phase difference control speeds.
は第４項に記載の位相差制御装置において、入力論理ゲ
ートおよび制御論理ゲートをＮＡＮＤか″ートとし、デ
ィジタル位相差保持回路をカウンタとし、インパルス発
生回路を微分回路としたことを特徴とする位相差制御装
置。(5) In the phase difference control device according to claim 1, 3, or 4 of the utility model registration claim, the input logic gate and the control logic gate are NAND gates, and a digital phase difference holding circuit is provided. A phase difference control device characterized in that a counter is used and the impulse generating circuit is a differentiating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8152085U JPS614202U (en) | 1985-05-30 | 1985-05-30 | Phase difference control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8152085U JPS614202U (en) | 1985-05-30 | 1985-05-30 | Phase difference control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS614202U true JPS614202U (en) | 1986-01-11 |
| JPS6343526Y2 JPS6343526Y2 (en) | 1988-11-14 |
Family
ID=30628378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8152085U Granted JPS614202U (en) | 1985-05-30 | 1985-05-30 | Phase difference control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS614202U (en) |
-
1985
- 1985-05-30 JP JP8152085U patent/JPS614202U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6343526Y2 (en) | 1988-11-14 |
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