JPS614235U - Signal processor input/output control device - Google Patents

Signal processor input/output control device

Info

Publication number
JPS614235U
JPS614235U JP8606984U JP8606984U JPS614235U JP S614235 U JPS614235 U JP S614235U JP 8606984 U JP8606984 U JP 8606984U JP 8606984 U JP8606984 U JP 8606984U JP S614235 U JPS614235 U JP S614235U
Authority
JP
Japan
Prior art keywords
input
signal processor
output
output control
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8606984U
Other languages
Japanese (ja)
Inventor
和長 井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp filed Critical Pioneer Corp
Priority to JP8606984U priority Critical patent/JPS614235U/en
Publication of JPS614235U publication Critical patent/JPS614235U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロック図、第２図は
第１図中の各部の状態を示すタイミング図、第３薗は従
来例を示すブロック図、及び第４図は第３図中の各部の
状態を示すタイミング図である。 １・・・・・・シグナルプロセッサ、２・・・・・・入
出力装置、４・・・・・・入出力コントローラ、１０・
・・・・・比較回路。Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing diagram showing the states of each part in Fig. 1, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a FIG. 3 is a timing diagram showing the states of each part in the figure. 1... Signal processor, 2... Input/output device, 4... Input/output controller, 10.
...Comparison circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デジタル信号からなるデータを処理するシグナルプロセ
ッサと、前記データの前記シグナルプロセッサへの入力
及び前記シグナルプロセッサから′の出力を行う入出力
手段と、前記シグナルプロセッサ及び前記入出力手段に
入出力制御信号を加えて前記シグナルプロセッサのデー
タの入出力を制御する入出力コントローラとを有するシ
ステムに５おいて、前記シグナルプロセッサがプログラ
ムの実行に同期して発生するタイミングパルスと、前記
入出力コントローラが他のクロツクに同期した前記入出
力制御信号に同期して発生する別の制御信号とを比較し
、前記タイミングパルスと前記別の制御信号とのタイミ
ングずれの検出により前記シグナルプロセッサ又は前記
シグナルプロセッサ及び前記入出力コン上ローラの両方
をリセットする信号を発生する比較手段を備えることを
特徴とするシグナルプロセッサの入出力制御装置。a signal processor for processing data consisting of digital signals; input/output means for inputting the data to the signal processor and outputting the data from the signal processor; and input/output control signals for the signal processor and the input/output means. In the system 5, further comprising an input/output controller that controls data input/output of the signal processor, the signal processor generates a timing pulse in synchronization with the execution of a program, and the input/output controller generates a timing pulse generated in synchronization with the execution of a program. The input/output control signal synchronized with the input/output control signal is compared with another control signal generated in synchronization with the signal processor, or the signal processor and the input/output are detected by detecting a timing deviation between the timing pulse and the other control signal. 1. An input/output control device for a signal processor, comprising comparison means for generating a signal for resetting both controller and rollers.
JP8606984U 1984-06-12 1984-06-12 Signal processor input/output control device Pending JPS614235U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8606984U JPS614235U (en) 1984-06-12 1984-06-12 Signal processor input/output control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8606984U JPS614235U (en) 1984-06-12 1984-06-12 Signal processor input/output control device

Publications (1)

Publication Number Publication Date
JPS614235U true JPS614235U (en) 1986-01-11

Family

ID=30637034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8606984U Pending JPS614235U (en) 1984-06-12 1984-06-12 Signal processor input/output control device

Country Status (1)

Country Link
JP (1) JPS614235U (en)

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