JPS61433U - Generator parallel input control device - Google Patents
Generator parallel input control deviceInfo
- Publication number
- JPS61433U JPS61433U JP8383984U JP8383984U JPS61433U JP S61433 U JPS61433 U JP S61433U JP 8383984 U JP8383984 U JP 8383984U JP 8383984 U JP8383984 U JP 8383984U JP S61433 U JPS61433 U JP S61433U
- Authority
- JP
- Japan
- Prior art keywords
- generator
- voltage
- closing
- control
- waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例による並列投入制御装置のブ
ロック図、第２図は同上装置の動作説明用の波形図であ
る。
１・・・計算機、２・・・ビート電圧波形メモリ、１１
・・・発電機、１２・・・遮断機、１３・・・エンジン
、−２１・・・母線、２２・・ゼ〒ト電圧検出回路、Ｆ
Ｂ・・・母線周波数、ＶＢ・・・母線電圧、ＶＢＴ・・
・ビート電圧、ＦＧ・・・発電機周波数、ＶＣ・・・発
電機電圧。FIG. 1 is a block diagram of a parallel input control device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the same device. 1... Calculator, 2... Beat voltage waveform memory, 11
... Generator, 12 ... Circuit breaker, 13 ... Engine, -21 ... Bus bar, 22 ... Zet voltage detection circuit, F
B...Bus frequency, VB...Bus voltage, VBT...
・Beat voltage, FG... Generator frequency, VC... Generator voltage.
Claims (1)
線周波数と微少な一定差を保つように制御する揃足制御
手段と、この揃足制御が行なわれているときの上記発電
機出力と母線系統とのビート電圧波形に許容誤差範囲を
加味した基準波形を記憶したメモリと、上記揃足制御と
並行して上記ビート電圧を高速でサンプリングし、位相
同期点からの各サンプル値を上記メモリの基準波形とを
順次比較し、ある位相同期点から所定時間の間、各サン
プル値が基準波形の許容誤差範囲内に収まっていたとき
投入指令信号を発するビート電圧波形比較手段とを備え
、上記投入指令信号に応答して並列投入用遮断器を投入
制御するように構成した発電機の並列投入制御装置。an equal footing control means for controlling the generator voltage to be equal to the bus voltage and a generator frequency to maintain a slight constant difference from the bus frequency, and the generator output and the bus line when the equal footing control is performed. A memory stores a reference waveform that takes into account the allowable error range for the beat voltage waveform with the system, and the beat voltage is sampled at high speed in parallel with the above-mentioned even foot control, and each sample value from the phase synchronization point is stored in the memory. beat voltage waveform comparison means that sequentially compares the voltage waveform with a reference waveform and issues a closing command signal when each sample value is within the tolerance range of the reference waveform for a predetermined period of time from a certain phase synchronization point; A generator parallel closing control device configured to control closing of a parallel closing circuit breaker in response to a command signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8383984U JPS61433U (en) | 1984-06-06 | 1984-06-06 | Generator parallel input control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8383984U JPS61433U (en) | 1984-06-06 | 1984-06-06 | Generator parallel input control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61433U true JPS61433U (en) | 1986-01-06 |
| JPH0134525Y2 JPH0134525Y2 (en) | 1989-10-20 |
Family
ID=30632824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8383984U Granted JPS61433U (en) | 1984-06-06 | 1984-06-06 | Generator parallel input control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61433U (en) |
-
1984
- 1984-06-06 JP JP8383984U patent/JPS61433U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0134525Y2 (en) | 1989-10-20 |
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