JPS6143885A - Scan converter - Google Patents

Abstract

PURPOSE:To scale down memory by providing a memory device which is of two- line jumping scan system for using a field of (2N+1)/2 lines and has (N+1) lines, patrolling the address of (N+1) lines and reading repeatedly twice during writing the address of one line so as to obtain a signal of a sequential system. CONSTITUTION:When a video signal subjected to the jumping scan is written and read by patrolling the address with use of a memory device having an address of 263 lines, it is assumed that the address concerned where a line of a number N or N' is written is M. The information of the address M is read out at the first time, but it is the information before 263 lines. Then the information read out from the address M at the second time, is the information of the line N written at the 2nd reading. When the line number in the midst of writing corresponds to an N' of the 2nd field, at the first time the information of the line N in the 1st field is read out, and at the second time a video signal of the line N' written at the 2nd reading is read out. Thus a picture can be composed by a sequential scan having lines twice in one field of the jumping scan system.

Description

[Detailed Description of the Invention] A: Industrial Field of Application The present invention converts a television signal transmitted in an interlaced scanning system into a progressive scanning system, removes various vulgarities caused by the interlaced scanning system, such as line flicker, and The present invention relates to a scan conversion device used to reproduce high-quality images.

(b) Prior Art FIG. 6 shows a schematic block diagram of a conventional scan converter for converting a television video signal based on the interlaced scanning method into a television video signal using the full progressive scanning method.

In Fig. 6, an input spectral image signal (vl) by 2:1 interlaced scanning that has been subjected to video detection is input to an A/D converter (ADJ), which converts it into a digital signal and converts it into a digital image. The signals are sequentially written into a storage device (Mg) such as a semiconductor memory. Also, the storage device (ME) has a time-sharing period for writing input data and a period for writing data written during this writing period. A continuous reading period is provided, whereby converted and combined digital signals are sequentially read out and output.The digital signals read from the memory device (MM) are input to the D/A converter (DA). q(TG
Jt! A timing signal generator generates timing signals for each 1tt-operation in this system.

This conventional example shows only one signal system,
It can be used as is in black-and-white television receivers that handle only luminance signals, and in color television receivers, it requires processing of discrete signals (luminance signals and color difference signals or primary color signals of red, green, and blue). In that case, a circuit as shown in FIG. 6 may be applied to each signal.

Next, an explanation will be given of the operation of the conventional scan conversion facility mentioned above with reference to the 71st meeting.

In FIG. 7, (A) is a video signal waveform transmitted in 2:1 interlaced scanning, a vertical deflection current waveform in te++a interlaced scanning, and H is a timing diagram showing the operation timing of the storage device. In Fig. 7 (4), period 1B indicates one horizontal scanning period in interlaced scanning, in Fig. 7(b), period 1v indicates one vertical scanning period, and in Fig. 7H, period 1H indicates one horizontal scanning period in sequential scanning. One vertical scanning period is the same as in interlaced scanning and sequential scanning, but one horizontal scanning period in progressive scanning is half of that in interlaced scanning. Furthermore, l! In Figure 7, to simplify the explanation, the ratio of horizontal and vertical scanning periods is 0.
j+1 near, 5, which is selected to be very small, but 2:1
It can be seen that the interlaced scanning condition is satisfied, and in this case, two vertical scans, that is, two fields constitute one screen consisting of 15 scanning lines.

In FIG. 7 PS, the horizontal axis represents time, the vertical axis represents the address of the storage device, the solid line represents the read cycle timing of the storage device, and the line #J represents the write timing.

As can be seen from this figure, the storage device f consists of video signal information for each line in the field? When writing, after writing all the signals for -line, empty the address for -line (in other words, write the video signal information for the next line from J without writing), and repeat the operation. When writing each line in a field, the address for each line that was not written in the previous field is written sequentially, and the video signal information written in this way is read out sequentially. It is controlled by a timing signal VC from a timing signal generator (TO) to continuously read out pages at twice the writing speed.

For example, in FIG. 7(C), the operation of the storage device during one horizontal scanning period A within a certain field of the video signal 1 (+) that is currently being written is considered. '(Period a-a is half of period A] The information written in addresses ADa-ADa' is read out.The information butterfly written in this address AD-ADa' is the seventh Information on the write period shown by extending the ^Da-ADa' period to the left in Fig. e, that is, the video signal information of the 1H period B in the previous field. In this period @AVC, video signal information is read out to the 1H period which is currently being written.The information read out from the storage device (ME) in this way is as follows:
The video signals of the 1H period of the two fields become information arranged alternately within one field, and this signal information? The vertical deflection wave number is the same as in the case of the interlaced scanning method, and the horizontal deflection frequency is twice as high as that in the case of the interlaced scanning method, and is displayed on the cathode ray tube screen. It is possible to reproduce an image consisting of 15 scan lines without scanning, thereby converting from interlaced scanning to progressive scanning.

In the above, for convenience of explanation, the ratio of the horizontal scanning period to the vertical scanning period was set to 1 = 11.5, but in the current NTSC system, the ratio is 1:262.5, and the signal of the horizontal scanning period of fc1 is It has been explained that writing and reading are all performed in a minimum unit, and that all five writings are performed simultaneously on the same storage device, but these operations are actually performed in a time-sharing manner, but will not be described in detail here.

By the way, in the above conventional example, r[As can be seen from FIG. 7H, addresses for Hx-x are required as addresses of the storage device. In other words, it can be seen that the total number of addresses for loading video signal information for one frame is the total number of addresses for the entire storage device. Needed.

For example, in the scan converter 8 position shown in Figure 1, the number of nippings in A/D converter 4 CA D J is VC910 times in one horizontal scanning period (the tapping sampling frequency is set to 4 of the color subcarrier in color television). Assuming that the frequency is twice as high and the amount of information for one pixel in the NTSC video signal is made up of 8 bits, the amount of information that should be stored PζP-910X525X8'=467KB[
This requires a storage table flit that can store a very large amount of information, which not only increases the cost of the storage device, but also increases the size of the storage device itself. The drawback is that the storage device occupies a large proportion of the space.In addition, P. 147 of Proceedings of the 11982 National Conference of the Television Society J, edited by the Japan Society of Television Television, published on June 20, 1982. ~P, 148111m also describes a scan converter, but does not provide any details on how to use the memory specifically.

Points to be Solved by the Invention This invention has been devised to eliminate all of the above-mentioned drawbacks, and its entire purpose is to provide a low-cost, compact scan converter.

) Problem? Solved/) 7th means 2N+1 In the present invention, each field is composed of 2 fins, and the video signal of 2 fields which are in an interlaced scanning relationship is made into 8 fields with the same wave number and twice the number of lines. In order to convert into a sequential television video signal, a memory having addresses corresponding to N+1 lines of the interlaced scanning video signal is provided, and the N+ addresses of this memory are
The addresses for one line are circulated, and each line of each field of the interlaced scanning video signal is sequentially convolved, and the address for each line of the memory where the insertion is being performed is 2 at twice the speed of writing
The storage device is controlled so as to read out data in sequence repeatedly.

(e) Effect: Due to the fact that the VCF 11 is configured as described above, among the information that is repeatedly read out from the storage device twice while the video signal information for one line of a certain field is written, the former information is currently This becomes video signal information for -line in the field before the field being written, and the latter information becomes video signal information for one line in the field currently being written.

(f) Example Hereinafter, the present invention will be explained with reference to all FIGS. 1 to 5.

The general configuration of the scan conversion device of the present invention is the same as that shown in FIG. 6, but the storage device controlled by the timing signal generator is different.

FIG. 1 is an operation timing diagram schematically showing the operation of the storage device according to the present invention. Waveform,? N indicates the operation timing of the storage device, and in this Fig. 1 P'4, the horizontal axis is 111#'i time, the vertical axis is the address of the storage device, the solid line is the read timing of the storage device, and the broken line is the write timing of the storage device. are shown respectively. 1 fci as before
In Fig. 1A, period 1H indicates one horizontal scanning period in the interlaced scanning method; One vertical scanning period is the same (-second) for interlaced scanning and sequential scanning, but one horizontal scanning period for sequential scanning (IHJ is half that for interlaced scanning. Similarly to the example, in FIG. 1, the ratio of horizontal and vertical scanning periods is selected to be a1 near, 5 so as to satisfy the 2:1 interlaced scanning condition, and one line consisting of 15 scanning lines is formed by two vertical scannings. This will be explained assuming that it constitutes a screen.

2N+1 In this way, each field is composed of 2 lines (N is a natural number) [in the case of Figure 1, N-7 = 75 lines], and the video signals for 2 fields, which are interlaced with each other, are divided by the field frequency ( In order to convert into a sequential television video signal with the same vertical deflection frequency and twice the number of lines, 2N+1 to -N+1 lines of the interlaced scanning video signal are stored in the storage device used in the present invention. Minute C
In the case of FIG. 1, there are addresses of 8 lines (N-7), and addresses for these N+1 lines are circulated. Therefore, as shown in Fig. 1, the vertical deflection period (the period in which the IVJ and the storage device cyclically visit their addresses) do not match, and the video signal information stored in the storage device is limited to one line (one line).
8] minutes. And, the storage device stores one line of each field in the interlaced scanning method? While writing sequentially, is the video signal information in each address for one line? It is controlled so that it is read out in sequence by repeating twice at the writing speed. During these two readings, one of the reading information is the video signal information of the field immediately before the field currently being written, The other read information is video signal information of the current field currently being written.

Now, if we consider the operation of the storage device during one horizontal scanning period A in a certain field while referring to the 11th problem, we will consider the operation of the storage device during one horizontal scanning period A within the period A (this period a-a is half of the period A). In the period 1) IK equivalent) is the address ADa-ADa.
'IcmF is loaded and the next information is compared. This address A
The information written in D-A D a' is AD
, -ADa' section extended to the left and the broken line intersects, that is, one line of video signal information indicated by period B in the previous field, and this information is read out. In the period a-a, it appears that writing is in progress within this period A, and it is read out at twice the writing speed. Therefore, after converting the video signal information read out in this way into an analog signal, the vertical deflection By keeping the frequency the same as in the case of interlaced scanning, and setting the horizontal deflection frequency to twice that of the case of interlaced scanning, and displaying it on a display device such as a CRT, it is possible to sequentially scan images starting with interlaced scanning. This means that the image is converted into an image.

In this way, the storage capacity required for the storage device is
As can be seen from the maximum address value shown in the first prisoner, it is about half of the storage device in the conventional example explained in FIG. 910 times during the scanning period, -1iI
8i purple information writing power x8 bits, the amount of information to be stored P' is P-910x236
34KB (byte) Next, we will explain how sequential scanning is performed correctly when the present invention is fully applied to the NTSC system, with reference to Figures 2 to 4. 〇 Figure 2 is 2:1 interlaced scanning? This shows the signal waveforms of the first and second fields of the NTSC video signal, in which VB indicates the vertical retrace period, and the ratio of the vertical deflection period to the horizontal deflection period is 262.5: 1 □ Also, for the convenience of explanation below, the following numbers are given in Fig. 2. That is, one complete horizontal scanning period that appears at the beginning of the vertical retrace period of the first field is designated as ■; Each subsequent horizontal scanning period is sequentially numbered as ■■..., and the complete one horizontal scanning period at the end of the first field (
Similarly to Φ, the VC second field has a horizontal scanning period O
The first complete horizontal scan period following ? ■ Binding,
For each subsequent horizontal scanning period, the right shoulder of the number...
Above with CFZ J! If the horizontal scanning periods of the 41st field are sequentially numbered before the horizontal scanning period ■, the last horizontal scanning period of the second field will be Oi.

Figure 6 shows the scanning lines formed on the cathode ray tube screen when video signals numbered as shown in the figure are subjected to interlaced scanning.
) is the second field, and the figure N is the shape of one frame that overlaps the first field and the second field? In the figure shown, it can be seen that one screen is constructed by interlaced scanning of two fields like this. Now, is this kind of interlaced scanning? ? 1-now video signal, 2
Using all the memory devices which have addresses corresponding to 66 lines, write and read data as shown in Figure 1 by circulating these addresses. Let us consider the operation of the Tit device when the corresponding address of the storage device to which this line is written is M in the line numbered N or N' (in FIG. 4, N is indicated by a circle).

At this time, the information written in this address M is first read from the storage device, but this information is one cycle before the address in the storage device, in other words, 263 lines before the address. This is video signal information.

In other words, if the number of the line currently being written corresponds to H in the first field, the field before it is the second field, and each line in this second field has a number from yrrl■' to @. (This means that the video signal information of the line (N-1) of the second field is read out.)The information that is read out from address M on the line H for the second time is this second time. This is video signal information of line N written at the time of reading.

Similarly, if the number of the line currently being written corresponds to N in the second field, it is the previous field, the first field, and each line in the first field is Since the numbers are numbered up to ■, the video signal information of line H of the 81st Vcb first field is read out, and the video signal of line N written at the time of this second reading is read out the second time. Ru.

In this way, during one field period of interlaced scanning, data from the storage device is always..., N-1, (N-1), N
, N, N+1, (N+iJ...), so when these video signal information are displayed on a cathode ray tube screen, one field period of the interlaced scanning method [2 times as many lines? The entire image can be constructed by scanning.

FIG. 5 is a block diagram showing a more detailed embodiment of a scan conversion device for implementing all of the above-described scan conversion operations.

In this FIG. circuit, +7
1 is a phase comparator circuit, 181 is a first counter with a frequency division ratio of 28.6 for the center station wave number of the wave number to be transmitted, +101 is a second counter with a - division ratio, and IID has a frequency division ratio of □. @
3 counters.

Standard NTS supplied from outside as shown in Figure 2 [11]
C method composite steel signal 1alFXA/D converter fi
The sampling clock (GI
The data is quantized by VC and input as 8-bit parallel data lbl to the serial/parallel converter 121 by the timing signal +hllC. This converter+21i converts serial signals of 8 bits each for 1 pixel into "14 pixels, or 8
By this conversion to x14 bit parallel signal,
Note: The speed of data supplied to the device (31) is reduced to allow the use of the dynamic memory described above.The data thus reduced in speed is 1.02M.
112 bits χ by Hz timing pulse lit
Storage capacity for 16? The address signal (
kl and write/read control signal 1jl,
The data written in the memory device (31), which is written sequentially, is read out using the address signal +kl and the read control signal +jl, and is supplied to the parallel-to-serial converter +41VC as the signal +dl. At this time, the write operation is performed. Two read operations are performed for one read operation, but since this operation has already been described in the explanation of FIG. The data parallel-to-serial converted by the converter (4) is converted into an analog signal in the D/Alj converter (5) at a frequency of 28.6 MH2, which is twice the sampling station wave number, and the horizontal frequency is 28.6 MH2, which is twice the frequency of the sampling station wave number. It is supplied to the display device as a video signal [fl] with double the frequency.

On the other hand, the composite video signal (al) is also input to the synchronization separation circuit (61), and the horizontal synchronization signal fat and vertical synchronization signal +fi+ are taken out by this circuit (6).This vertical synchronization signal 1nl
d is supplied to the vertical deflection circuit and the third counter ill of the display device.The horizontal synchronizing signal fat is also input to the phase comparator circuit (7), and is output from the VCO ()l+.
The phase of the signal with the radio wave number of 8.6 MB2 is compared with the horizontal period signal 1r+ which is divided by the first and second counters f91111. The output 1p+ obtained from this comparison result is supplied as a control signal to the V C0 (RIK).
CO darkness is in phase with the horizontal synchronization signal (o) 28.6
It operates as an oscillator that oscillates at the radio frequency of MH2, and its output is used as a main clock of 28.6 MHz <q, 1. At the same time, the frequency-divided output H of the second counter (91) similarly becomes a horizontal synchronization signal whose phase matches that of the horizontal synchronization signal (0+.
is a signal with one horizontal opening period of 28 minutes, and is used as a signal for horizontal synchronization of the display device.

The third counter (IIIvC is supplied with the vertical synchronizing signal 1nl, but when this vertical synchronizing signal (nl is input), the third counter (111 is inputted for 7 horizontal scanning periods within the vertical retrace period of the composite video signal 1al). (i.e., 7 counts)).

The second counter (1) is configured to count 65, and the phase control loop allows the 65th count to be V
cllTIIg4. Also, from the second kakuntal ltl, the lower 6 bits are used to determine 0 to 63? The count value to be expressed is supplied as a lower address value, that is, a column address, of the address signal fKl provided to the memory table f11t31Vc. It should be noted that the upper address value of the address signal applied to the storage device +31 is supplied from the row address light @3 counter.

0 to 64 as the 0!2 counter 1lja count value
Since the lower 6 bits are used as the lower address of the storage device as described above, when the counter value is 0 and 64, the same lower address value is supplied to the storage device information is rewritten at the same location, resulting in a loss of read information, but this information corresponds to or near the horizontal synchronization signal in the composite video signal, and is worthless information as video signal information. It is.

Similarly, the sixth counter 11υ is stored in the memory @(3+i
c The supplied address signal also outputs the same address value by 7 counts due to the arrival of the vertical synchronization signal fnl.
2. In this case as well, the video signal information near the vertical synchronization signal is worthless information, and it can be understood that there is no benefit in operating in this manner.

With the above configuration, the recording device +31 operates with 263 horizontal scanning periods as one cycle, and
This memory device #(nAD=+65-1 for 3I)X(263-7 no 64X25
6-16! It becomes possible to use a semiconductor memory or the like having an address of +8+16.

At this time, the total capacity of the storage device clf.

c=t 4W8XI B (pit)===14×16 [byte] t e11), for example, the storage device can be constructed by using 28 semiconductor memories of 4×16 bits.

(F) Effects of the Invention According to the present invention, the capacity of the storage device required when converting an interlaced scanning television video signal into a progressive scanning television video signal can be reduced, resulting in a compact and low-cost system. Scan converter can be obtained 0

[Brief explanation of drawings]

FIG. 1 shows the basic structure of the scan converter according to the present invention! The figure shown in the time chart for complete explanation, Figure 2 is the @ of NTEJC method.
Figure 3 shows the vertical retrace period of the 1st field and the 2nd field, and the waveforms showing the video signals before and after that. FIG. 4 is an explanatory diagram of the operation of the apparatus of the present invention, FIG. 5 is a block 1 diagram showing the configuration of an embodiment of the scan conversion apparatus of the present invention, and FIG. 6 is a diagram showing the entire screen including fields. FIG. 7 is a schematic block diagram of a conventional scan conversion device, and is an explanatory diagram of its operation. tl+...A/D converter, (2)...Serial to parallel converter, (31...Storage device, (4)...Parallel to serial converter, (5)...D/ ^Converter, Machine (6)...Synchronization separation circuit, (7)...Phase comparison circuit, (Otherwise...Voltage control monitor, (9)...1st counter, 10th... 2 counter, (il+...3rd counter.

Claims (1)

[Claims] (1) A sequential television video signal in which each field is composed of (2N+1)/2 lines, and the two fields' worth of video signals are interlaced with each other, and the field frequency is the same and the number of lines is doubled. The apparatus includes a storage device having addresses corresponding to N+1 lines of the interlaced scanning video signal, circulates the addresses of the N+1 line of the storage device, and converts the interlaced scanning video signal into One line of each field in each signal field is sequentially written, and the address of each line of the memory where the writing is being performed is read out sequentially twice at twice the writing speed. A scan conversion device characterized in that the television signal of the sequential system is obtained by the readout.