JPS6145656A - Auxiliary equipment for detecting and reflecting remote code error - Google Patents

Abstract

PURPOSE:To simplify the constitution by counting an error code in a reception data transmitted from the remote side, replacing the count value with transmission data supplied from a data terminal device and transmitting an output of a test code detection circuit to the remote side. CONSTITUTION:When a test code is transmitted from a remote side, a test code detection circuit 14 inputs the test code as a reception data signal RD and the reception is detected by supervising an output of an error code detection circuit 13 as an input. When a test code is detected by the circuit 13, the data RD outputted to a data terminal device 5 is stopped to turn on a test state display TI to switch a transmission output data to the 2nd data transmission reception device 3 is switched into an output of an error code count circuit 15. The circuit 15 generates pulses having the same number as that of error codes according to a transmission timing signal. Thus, the remote side detects an error code on a transmission line by transmitting a test code and counting the pulse number in reception data.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a test device for testing data transmitters and receivers, etc.
In particular, the present invention relates to a remote code error detection and loopback auxiliary device that detects error codes in received data by remote control and loops back the result.

[Prior art]

Data transmitters and receivers in general, and synchronous data transmitters and receivers in particular.

The data transmitting device selects either the Thai blowfish signal (hereinafter referred to as ST1) supplied from the data terminal as a transmission timing signal or the transmission timing signal and reception timing signal generated by the data transmitting and receiving device itself. One of the timing signals (hereinafter referred to as Si2) is selected and used as the transmission timing signal. Also,
The reception timing signal extracts the timing component from the signal or data signal on the transmission path and reproduces the reception timing signal synchronized with the transmission side timing signal.This regenerated reception timing signal (hereinafter referred to as RT)
generally has some fluctuation (jitter) 〇And, in a system that performs data communication by placing the above general data transmitting and receiving devices facing each other, the receiver data is returned by remote control, and data is transmitted at one end. Transmission tests are often conducted to measure quality. In such cases, if there is a loopback auxiliary device that loops back received data via remote control, the above transmission tests can be easily performed.

However, as described above, since the transmission timing is S T 1 or Si2 selected by the system, the reception timing and the transmission timing are not necessarily synchronized. Furthermore, even when the far end side performs a dependent operation, there is jitter in the reception timing. Therefore, to wrap the data,
Simply folding received data back into transmitted data is not sufficient.

゛The first example is an example of a system using a remote call back assist device.
To explain it as shown in the figure, in the figure, 1 is a communication processing device;
2 is a first unit that exchanges information with this communication processing device 1;
3 is a second data transmitting/receiving device connected to the data transmitting/receiving device 2 via a transmission line 6;
5 is a remote return assisting device connected to the output side of the second data transmitting/receiving device 3, and 5 is a data terminal device which receives the output of the remote return assisting device 4 as an input. Further, T indicates the flow of data during the remote loopback test.

The system shown in FIG.
This system performs data communication by arranging data transmitting/receiving devices 2 and 3 facing each other, and is configured to detect code errors in received data by remote control from one end and return the results.

In the system configured as described above, it is assumed that the second data transmitting/receiving device M3 operates with dependent timing. If the first and second data transmitting/receiving devices 2 and 3 operate at independent timings, the loopback shown at 9, which shows the data flow, is impossible.

Therefore, in order to support a variety of systems, the remote return assist device 4 requires timing switching, buffering, and a high-precision oscillator that match the system configuration. There was a drawback that it was not.

[Object and structure of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The present invention has a simple configuration to detect an erroneous code even when the transmission and reception timings are not synchronized. It is an object of the present invention to provide a remote code error detection and folding aid that can be used.

In order to achieve such an object, the present invention provides an erroneous code detection circuit that receives n received data supplied from a second data transmitting/receiving device and detects an error code in the received data;
A test code detection circuit receives the received data and the output of the erroneous code detection circuit and detects a test code, and receives the output of the erroneous code detection circuit and counts the number of erroneous codes and determines the selected transmission timing. and a switching circuit that switches the output of the counting circuit and the transmission data supplied from the data terminal device and outputs the same to the second data transmitting/receiving device, Accordingly, the output of the erroneous code detection circuit is output to the second data transmitting/receiving device instead of the transmission data of the data terminal device.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the remote code error detection and return assisting device according to the present invention, and only the parts necessary for explanation are shown.

In this Figure 2, 11m, 11b...11
9 is a receiver, 12a * 12b...12f is a driver, and 13 is an erroneous code detection circuit that receives received data RD supplied from the second data transmitting/receiving device 3 and detects an erroneous code in the received data. , 14 is received data RD
and a test code detection circuit that receives the output of the incorrect code detection circuit 13 and detects a test code; 15 is the incorrect code detection circuit 13;
An erroneous code counting circuit which receives the output of the erroneous code counting circuit 16 counts the number of erroneous codes and reduces the number of erroneous codes according to the selected transmission timing. A switching circuit (selector) 11 switches between the supplied transmission data SD and outputs the data to the second data transmitting/receiving device 3, and 11 is a transmission timing signal selection switch.

18& is an AND gate which receives the output of the receiver 11b and the output of the erroneous code detection circuit 13 and sends the logical product of these inputs to the erroneous code counting circuit 15;
takes the output of the test code generation circuit 14 and the output of the receiver tta as inputs, and calculates the AND of these inputs.
18a is an AND gate which inverts the signal and sends it as reception data RD to the data terminal device 5 through e, and 18a is a register signal from the output of the test code generation circuit 14 and the second data transmission/reception device 3''.
This is an AND gate which receives the output of the test status display TI via 11d, inverts the AND of these inputs via 12f, and sends it to the data terminal device 5 as the test status display TI.

The receivers 11m + 11b each receive the received data RD and the received timing signal RT from the second data transmitting/receiving device 3, invert these inputs, and send their respective inverted outputs to the incorrect υ code detection circuit 13 and the test code generation circuit 14. The inverted output of this receiver 11b is Drino? Fake data terminal device 5 reversed through 12e
The reception timing signal RT is configured to be sent out as a reception timing signal RT. The receiver 11e is the second data transmitting/receiving device 3
Inputs the received carrier CD from the dry I (1
The receiver 11e receives the timing signal ST3 from the second data transmitting/receiving device 3 and transmits it to the data terminal device 5 as a reception carrier CD.
is input, this input is inverted, and this inverted output is driver 1
The timing signal ST2 is inverted and sent to the data terminal device 5 as a timing signal ST2. Also,
The receiver 11f receives transmission data S from the data terminal device 5.
Switching circuit (selector) 1 which inputs D and inverts this input.
The receiver 11t receives the timing signal STI from the data terminal device 5 and inverts this input, and the inverted output is inverted via the driver 12b and sent to the second data transmitting/receiving device 3. timing signal S
It is configured to be transmitted as Tl. The switching circuit (selector) 16 is controlled by the output of the test code generation circuit 14, switches the output of the error code counting circuit 15 or the inverted output of the receiver 11f, inverts the switched output via the driver 12a, and generates the second data. The data is configured to be sent to the transmitting/receiving device 3 as transmission data SD. The transmission timing selection switch 1T receives the output of the receiver 11e, which receives the timing signal ST2, and the output of the receiver 111, which receives the timing signal STl, as inputs, switches these inputs, and sends the switching output to the error code counting circuit 15. Next, the operation of the embodiment shown in FIG. 2 will be explained. First, when detecting an erroneous code and performing loopback, a test code is sent from the remote side. This test code is the received data signal RD.
The received signal is input to the auxiliary device as follows, and reception is detected by monitoring the erroneous code detection circuit 13. When a test code is detected by this false code detection circuit 13,
Stop the received data RD output to the data terminal device 5,
The test status display TI is turned on, and the transmission output data to the second data transmitting/receiving device 3 is switched to the output of the error code counting circuit 15 by the switching circuit 16.

Next, the erroneous code counting circuit 15 generates the same number of pulses as the number of erroneous codes in accordance with the transmission timing signal. Here, it is assumed that the code error rate is sufficiently smaller than 1, so that the code error counting circuit 15 will not overflow.

Therefore, the remote side sends the test code and receives data R.
By counting the number of pulses in D, an erroneous code on the transmission line 6 shown in FIG. 1 can be detected.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, and shows an example in which an erroneous code is detected by comparing the output of the test code generation circuit 14 and the test code in the received data RD. It shows.

In FIG. 3, the same reference numerals as in FIG. The test code generating circuit 14 is configured to detect synchronization between the generated test code and the test code generating circuit 14. 22a
, 22b is a counter, and this counter 22m,
22b is configured to determine that a test code has also been received and start the test when the rate of occurrence of false detection pulses output from the bit pattern detection circuit 21 corresponding to the false code detection circuit 13 falls below a certain value. Further, if the received data RD has a mark code longer than a certain code length, the test is canceled, and if the damaged carrier CD is turned off, the test state is canceled.

23 is an exclusive OR circuit (EX-O
The output of the EX/0R 22 is input to the code counting circuit 15 and is also input to the counter 22a via the OR gate 24m. Further, the output of the counter 22& is input to the flip-flop 25, and the output of the counter 22b is input to the flip-flop 25 via the OR gate 24b.
The inverted output of the receiver 11c is input to the counter 22a via 24m and is input to the flip 70 via the OR gate 24b.
It is configured to be input to the knob 25. 26m inputs the inverted output of the receiver 11m and the output of the 7rip 70tube 25, and calculates the logical product of these two inputs.
The AND gate 26b inputs the inverted output of the receiver 11d and the output of the 7-lip 70-tub 25, and calculates the logical product of the two outputs and sends it to the data terminal device 5 as received data RD. This is an AND gate that is inverted and sent to the data terminal device 5 as a test status display TF.

FIG. 4 shows an example of a circuit extracted from the portion related to the test code generation circuit 14 in FIG.

In this Figure 4, 31m, 31b...31
1 is a 70-tube flip-flop that can be set and reset connected in cascade, and 32 inputs the output of this flip-flop 31e and the output of a 7-lip 70 tube 311, and inputs the output to the set terminal of the first-stage flip-flop 31m and outputs it. OUT exclusive OR circuit (EX-OR
). And flip-flop 31a t 31
The synchronizing signal 5YNC is supplied to b...311, and the flip 70 knobs 31a, 31b...
A reception timing signal RT is supplied to each reset terminal of 31i, and a test code is obtained at the output OUT.

FIG. 5 is an example of a circuit extracted from the part related to the error code counting circuit 15 in FIG.

In this FIG. 5, 41a, 41h, 41c are AND gates, 42m, 42b, 42c,
42d 7 rib flop, 4:lt and gate 41
an up/down counter which receives the output of 411 as an input; 44 is a comparator that detects the maximum and minimum values of this up/down counter 43;
5 is an oscillation circuit, and this oscillation circuit 45 is configured to oscillate at a frequency four times or more higher than the transmission/reception timing signal. 46 is a NOT circuit which receives the output of this oscillation circuit 45 as an input.

ERR is an erroneous detection pulse, RT is a reception timing signal, and these are input to an AND gate 41a, and the logical product output is supplied to a reset terminal of a clip-flop 42a, which is set by the output of the receiver 11h.
It is configured to

Further, the AND gate 41b is configured to input the output of the flip 70 toggle 42b and the output of the maximum value MAX of the comparator 44, and supply the logical product of these two inputs to the shift/down counter 43. It is configured to input the output of the 7O block 42d and the output of the minimum value MIN of the comparator 44, and supply the logical product of these inputs to the shift/down counter 43.

The timing signal ST is supplied to the reset terminal of the clip 70 knob 42c set by the output of the receiver 111, and is also supplied to the reset terminal of the flip 7a 7' 42e set by the output of the minimum value MIN of the comparator 44. and this 7 lip-flop 42e
The output is configured to be supplied to the data transmitting/receiving device 3 as transmission data SD.

In the false code counting circuit configured in this way, the comparator 44 detects the maximum and minimum values of the up/down counter 43, and since the test code is a pseudo-random pattern, the probability of false detection from the data signal is reduced. is very small.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the prefecture code can be detected with a simple configuration without using complicated means, even when the transmission and reception timing signals are not in a synchronized state. Since it is possible to realize a remote feedback auxiliary device sufficient to perform data transmission tests, the practical effect is extremely large.

[Brief explanation of drawings]

゛Fig. 1 is a block diagram showing an example of a system using a remote call-back assist device, Fig. 2 is a circuit diagram showing an embodiment of the remote code error detection callback assist device according to the present invention, and Fig. 3 is a block diagram showing an example of a system using a remote call-back assist device according to the present invention. 4 is a circuit diagram showing an extracted part related to the test code generation circuit in the embodiment of FIG. 3, and FIG. 5 is a circuit diagram showing an error code generation circuit in the embodiment of FIG. FIG. 2 is a circuit diagram showing an extracted portion related to a code counting circuit. 1... e communication processing device f, 2.3... data transmitting/receiving device, 5... data terminal device, 6... transmission line,
13... Erroneous code detection circuit, 14... φ Test code generation circuit, 15... Erroneous code counting circuit, 16#...
・Switching circuit, 21. Hit/bit pattern detection circuit.

Claims (1)

[Claims] a communication processing device; a first data transmitting and receiving device receiving the output of the communication processing device; a second data transmitting and receiving device connected to the first data transmitting and receiving device via a transmission path; A data terminal device connected to the output side of the data transmitting/receiving device is provided, and the first and second data transmitting/receiving devices are faced to perform data communication. In a remote loopback auxiliary device that detects code errors and loops back the results,
an error code detection circuit that receives received data supplied from the second data transmitting/receiving device as input and detects an error code in the received data; and an error code detection circuit that receives received data and the output of the error code detection circuit as input and detects a test code. a test code detection circuit that receives the output of the error code detection circuit, counts the number of error codes and decrements it in accordance with the selected transmission timing; a switching circuit configured to switch the output data from the error code detection circuit to the second data transmitting/receiving device in place of the data transmitted by the data terminal device according to the output of the test code detection circuit; A remote code error detection and return auxiliary device, characterized in that it outputs to a second data transmitting/receiving device.