JPS6149619A - Power source switching device - Google Patents
Power source switching deviceInfo
- Publication number
- JPS6149619A JPS6149619A JP59169053A JP16905384A JPS6149619A JP S6149619 A JPS6149619 A JP S6149619A JP 59169053 A JP59169053 A JP 59169053A JP 16905384 A JP16905384 A JP 16905384A JP S6149619 A JPS6149619 A JP S6149619A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- resistor
- power supply
- output
- stabilized power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 24
- 230000006641 stabilisation Effects 0.000 claims description 4
- 238000011105 stabilization Methods 0.000 claims description 4
- 230000000087 stabilizing effect Effects 0.000 description 18
- 239000003990 capacitor Substances 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、データ処理装置に適する現用・予備電源切換
装置に関する。特に、この装置の現用電源と予備電源と
の切換制御手段に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a working/standby power supply switching device suitable for a data processing device. In particular, the present invention relates to means for controlling switching between a working power source and a standby power source for this device.
従来例現用・予備電源切換装置は、第２図に示すように
構成されている。この図で直流安定化部４および２４の
端子８および２８は過不足電圧検出用端子であり、これ
は非安定化直流ＰＵＩおよびＰＵ２の出力端子ｌＯおよ
び３０にそれぞれ接続され、また直流安定化部４および
２４の安定化用電圧検出端子９および２９は逆電流阻止
用ダイオードＤ４１お不足電圧検出用端子８および２８
と安定化用電圧検出端子９および２９とが同一点で接続
されていない。A conventional active/standby power supply switching device is constructed as shown in FIG. In this figure, the terminals 8 and 28 of the DC stabilizing units 4 and 24 are terminals for detecting over/under voltage, which are connected to the output terminals 1O and 30 of the non-stabilized DC PUI and PU2, respectively. Stabilizing voltage detection terminals 9 and 29 of 4 and 24 are reverse current blocking diodes D41 and terminals 8 and 28 for undervoltage detection.
and the stabilizing voltage detection terminals 9 and 29 are not connected at the same point.
この接続により直流安定化電源回路ＰＵＩおよびＰＵ２
のいずれの回路で電圧異常が発生したかの判定が行われ
、故障側の回路が切り離される。This connection connects the DC stabilized power supply circuits PUI and PU2.
A determination is made as to which circuit in which the voltage abnormality has occurred, and the faulty circuit is disconnected.
このような従来例現用・予（Ｉｉｉ電圧切換装置では、
ダイオードＤ４１およびＤ４２の順方向電圧降下の変動
および直流安定化電源回路ＰＵＩおよびＰＵ２と負荷４
９間の配線に生ずる電圧降下の変動などのため北直流安
定化電源回路ＰＵＩおよびＰＵ２の出力電圧異常検出の
精度が不安定になり、検出レベルが低すぎることによる
誤動作頻度の増大、および検出レベルが高すぎることに
よる負荷装置の早期劣化または損傷を招（欠点があった
。In such a conventional example of current/preliminary voltage switching device,
Fluctuations in forward voltage drop of diodes D41 and D42, DC stabilized power supply circuits PUI and PU2, and load 4
Due to fluctuations in the voltage drop that occurs in the wiring between 9 and 9, the accuracy of output voltage abnormality detection of the north DC stabilized power supply circuits PUI and PU2 becomes unstable, and the detection level is too low, resulting in an increase in the frequency of malfunctions and the detection level. Too high a temperature can lead to premature deterioration or damage to the load equipment (a drawback).
本発明は、この欠点を解決するもので、安定化制御の機
能を損なうことなく、高精度で現用・予備の各々の直流
安定化電源回路の出力電圧異常を検出することができる
手段を備えた現用・予備電圧供給装置を提供することを
目的とする。The present invention solves this drawback by providing means that can detect output voltage abnormalities of each of the current and standby DC stabilizing power supply circuits with high precision without impairing the stabilization control function. The purpose is to provide working and standby voltage supply equipment.
本発明は、それぞれ直流安定化部を含む二つの直流安定
化電源回路を備え、その二つの直流安定化電源回路には
それぞれ、外部直流電源の非接地側の端子に接続された
入力端子と、この外部直流電源の接地側の端子および外
部負荷の接地側の端子に接続された接地端子と、出力端
子と、過電圧および不足電圧を検出する第一の検出端子
と、安定化電圧を検出する第二の検出端子とを含み、上
記各出力端子と、上記外部負荷の非接地側の端子との間
にそれぞれ出力電流の方向に順方向に接続されたダイオ
ードを備えた電源切換装置で、前述の問題点を解決する
ための手段として、上記二つの直流安定化電源回路には
、それぞれ、上記第一の検出端子と上記第二の検出端子
とがそのコレクタに接続され、上記出力端子にそのエミ
ッタが接続されたトランジスタと、このトランジスタの
コレクタと上記接地端子との間に挿入され、直列接続さ
れた第一の抵抗器および第二の抵抗器と、上記出力端子
にその一端が接続された第三の抵抗器の出力力（上も己
第四のｔ氏抗２…と上言己第五の１氏Ｉ冗器のと、上記
トランジスタのベースにその一端が接続された第五の抵
抗器と、この第五の抵抗器の他端と上記第三の抵抗器の
他端との間に挿入された第四の抵抗器と、上記第一の抵
抗器と上記第二の抵抗器との接続点がその非反転入力に
接続され、そ安定化電源回路の比較器の反転入力が他方
の直流 虫接続点に接続された比較器とを備え
、一方の直流安定化電源回路の第三の抵抗器と第四の抵
抗器との接続点に接続され、また、上記第一の抵抗器と
′上記第二の抵抗器の接続点が上記負荷端
子の他方の端子に接続されたことを特徴とする。The present invention includes two DC stabilized power supply circuits each including a DC stabilization section, and each of the two DC stabilized power supply circuits has an input terminal connected to a non-grounded terminal of an external DC power supply. A grounding terminal connected to the grounding terminal of the external DC power supply and the grounding terminal of the external load, an output terminal, a first detection terminal for detecting overvoltage and undervoltage, and a first detection terminal for detecting stabilized voltage. 2 detection terminals, and diodes connected in the forward direction in the direction of output current between each of the output terminals and the non-grounded terminal of the external load. As a means to solve the problem, each of the two DC stabilized power supply circuits has the first detection terminal and the second detection terminal connected to its collector, and the emitter connected to the output terminal. a first resistor and a second resistor inserted in series between the collector of the transistor and the ground terminal, and a first resistor and a second resistor connected in series, and a second resistor whose one end is connected to the output terminal. The output power of the third resistor (the fourth resistor 2... and the fifth resistor 1 redundant, and the fifth resistor whose one end is connected to the base of the transistor mentioned above) and a fourth resistor inserted between the other end of this fifth resistor and the other end of the third resistor, and the first resistor and the second resistor. a third one of the one DC regulated power supply circuit, with the inverting input of the comparator of the regulated power supply circuit connected to the non-inverting input of the one DC power supply circuit; It is connected to the connection point between the resistor and the fourth resistor, and the connection point between the first resistor and the second resistor is connected to the other terminal of the load terminal. shall be.
過不足電圧検出および安定化制御用電圧検出を、半導体
スイッチの動作により、現用機では負荷端で行い、また
、予備機では直流安定化電源回路の出力端で行うように
動作する。Excess/deficiency voltage detection and stabilization control voltage detection are performed at the load end in the active unit, and at the output end of the DC stabilizing power supply circuit in the standby unit, by operating semiconductor switches.
以下、本発明実施例装置を図面に用いて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明実施例装置の構成を示す回路図である。FIG. 1 is a circuit diagram showing the configuration of an apparatus according to an embodiment of the present invention.
まず、本発明実施例装置の構成を第１図に基づいて説明
する。この実施例装置５０は、第一の直流安定化電源回
路ＰｕｔおよびＰＯ２と、ダイオードオア回路ＤＵＩと
を備える。ここで、第一の直流安定化電源回路ＰＵ１に
は、直流安定化部４と切換制御部１５とを備え、さらに
切換制御部１５には、比較器Ｚ１と、ＰＮＰ ）ランジ
スタＱ１と抵抗器Ｒ１〜Ｒ５とを備える。また、第二の
直流安定化電源回路ＰＵ２には、比較器Ｚ２１と、ＰＮ
Ｐ ｌ−ランジスタＱ２１と、抵抗器Ｒ２１〜Ｒ２５を
備える。First, the configuration of an apparatus according to an embodiment of the present invention will be explained based on FIG. This embodiment device 50 includes first DC stabilized power supply circuits Put and PO2, and a diode OR circuit DUI. Here, the first DC stabilized power supply circuit PU1 includes a DC stabilizing section 4 and a switching control section 15, and the switching control section 15 further includes a comparator Z1, a PNP transistor Q1, and a resistor R1. ~R5. Further, the second DC stabilized power supply circuit PU2 includes a comparator Z21 and a PN
It includes a Pl-transistor Q21 and resistors R21 to R25.
外部の非安定化電源１は直流安定化電源回路ＰＵｌの端
子２と３との間に挿入され端子３は共通電位に接続され
、非安定化電源２１は直流安定化電源回路ＰｔＪ２に端
子２２と２３との間に挿入され端子２３は共通電位に接
続される。また、直流安定化電源回路ｐｕｉ内では、端
子２と直流安定化部４の端子５とが接続され、端子３、
端子１２および直流安定化部４の端子６とが接続され、
端子１０と直流安定化部４の０ｊＡｊ子７とが接続され
る。また、直流安定化部４は安定化用電圧検出端子８お
よび過不足電圧検出用端子９を有し、本発明の特徴とす
る切換制御部１５は端子１）に抵抗器Ｒ１の一端が接続
され、抵抗器Ｒ１の他端にＰＮＰ ｌ−ランジスタＱ１
のコレクタが接続され、端子１０にＰＮＰ トランジス
タＱ１のエミッタが接続され、抵抗器Ｒ２は端子１）と
端子１２との間に挿入され、抵抗器Ｒ３は端子１０と端
子１４との間に挿入され、端子１４に抵抗器Ｒ４の一端
が接続され、抵抗器Ｒ５は抵抗器Ｒ４の他端とＰＮＰ
Ｉ−ランジスタＱｌのベースとの間に挿入され、抵抗器
Ｒ４の他端に比較器Ｚ１の出力が接続され、端子１）に
比較器Ｚ１の非反転入力が接続され、端子工３に比較器
Ｚｌの反転入力が接続され、端子８および９はＰＮＰ
）ランジスタＱ１のコレクタに接続される。直流安定化
電源回路ＰＵ２の構成は前述の直流安定化電源回路ＰＵ
ｌの構成と同一である。また、ダイオードオア回路ＤＵ
Ｉでは、端子４１にダイオードＤ４１のアノードが接続
され、端子４２．４３および４７にダイオード４１のカ
ソードが接続され、端子４４にダイオードＤ４２のアノ
ードが接続され、端子４２にダイオードＤ４２のカソー
ドが接続され、端子４７と端子４５．４６および４８と
の間にコンデンサＣ４１が挿入される回路ＰＵＩ、Ｐｔ
Ｊ２およびＤＵＩ間は端子１０と端子４１、端子１）と
端子４２、端子１２と端子４５、端子１３と端子３４、
端子１４と端子３３、端子３０と端子４４、端子３１と
端子４３、端子３２と端子４６とがそれぞれ接続される
。The external unregulated power supply 1 is inserted between the terminals 2 and 3 of the DC stabilized power supply circuit PUl, and the terminal 3 is connected to the common potential, and the unregulated power supply 21 is inserted between the terminals 2 and 3 of the DC stabilized power supply circuit PtJ2. 23, and the terminal 23 is connected to a common potential. Further, in the DC stabilizing power supply circuit pui, the terminal 2 and the terminal 5 of the DC stabilizing section 4 are connected, and the terminal 3,
The terminal 12 and the terminal 6 of the DC stabilizing section 4 are connected,
The terminal 10 and the 0jAj terminal 7 of the DC stabilizing section 4 are connected. Further, the DC stabilizing section 4 has a stabilizing voltage detection terminal 8 and an over/under voltage detection terminal 9, and the switching control section 15, which is a feature of the present invention, has one end of the resistor R1 connected to the terminal 1). , PNP l-transistor Q1 at the other end of resistor R1
The collector of the PNP transistor Q1 is connected to the terminal 10, the emitter of the PNP transistor Q1 is connected to the terminal 10, the resistor R2 is inserted between the terminals 1) and 12, and the resistor R3 is inserted between the terminals 10 and 14. , one end of resistor R4 is connected to terminal 14, and resistor R5 has a PNP connection with the other end of resistor R4.
The output of the comparator Z1 is connected to the other end of the resistor R4, the non-inverting input of the comparator Z1 is connected to the terminal 1), and the output of the comparator Z1 is connected to the terminal 3. The inverting input of Zl is connected and terminals 8 and 9 are PNP
) connected to the collector of transistor Q1. The configuration of the DC stabilized power supply circuit PU2 is the same as the DC stabilized power supply circuit PU described above.
The configuration is the same as that of l. Also, diode OR circuit DU
In I, the anode of the diode D41 is connected to the terminal 41, the cathode of the diode D41 is connected to the terminals 42, 43 and 47, the anode of the diode D42 is connected to the terminal 44, and the cathode of the diode D42 is connected to the terminal 42. , a circuit PUI, Pt in which a capacitor C41 is inserted between terminal 47 and terminals 45, 46 and 48
Between J2 and DUI, terminal 10 and terminal 41, terminal 1) and terminal 42, terminal 12 and terminal 45, terminal 13 and terminal 34,
The terminals 14 and 33, the terminals 30 and 44, the terminals 31 and 43, and the terminals 32 and 46 are connected, respectively.
次に、この実施例装置の動作を第１図に基づいて説明す
る。Next, the operation of this embodiment device will be explained based on FIG.
直流安定化電源回路ＰＵＩおよびＰＯ２のダイオード通
過後電圧はそれぞれ単独に予めほぼ同じ電圧値■３に設
定されている。ここで、非安定化電源ｌおよび２１がほ
ぼ同時に直流安定化電源回路ＰＵＩおよびＰＯ２に与え
られると、直流安定化電源回路ｐｕｔの出力電圧の立上
がり時間が直流安定化電源回路ＰＵ２の出力電圧の立上
がり時間より早ければ、ダイオード０４１が先に順バイ
アスになって、比較Ｒ３Ｚ２１の反転入力の電位が非反
転入力より高くなるので、トランジスタＱ２．は４通状
態になり、したがって直流安定化電源回路ｐｕ２はダイ
オードＤ４２のアノード電位がカソードとほぼ同電位と
なるように動作し、負荷４９に対し直流供給が行われな
い。このときには、直流化部２４の過不足電圧検出端子
２９は直流安定化電源回路ＰＵ２の出力端子３０の電位
に接続されている。一方、比較器Ｚ１の反転入力は比較
器Ｚ２１の出力により抵抗ｌＲ２４を介して低レベルに
もたらされるので、抵抗器Ｒ２３の抵抗値を適切に選ふ
と非反転入力よりもやや低くなる。ここで、トランジス
タＱ１は非薄通状態であるので、直流安定化電源回路ｐ
ｕｌはダイオードＤ４１のカソードの電位が電圧値■
、３に一致するように動作し、負荷４９に対して直流を
供給し現用機となる。このときには、直流安定化部４の
過不足電圧検出端子９は抵抗器Ｒ２を通してダイオード
Ｄ４１のカソードすなわぢ負荷端に接Ｖεされている。The voltages after passing through the diodes of the DC stabilized power supply circuits PUI and PO2 are individually set in advance to approximately the same voltage value (3). Here, if the unregulated power supplies 1 and 21 are applied to the DC stabilized power supply circuits PUI and PO2 almost simultaneously, the rise time of the output voltage of the DC stabilized power supply circuit put is the rise of the output voltage of the DC stabilized power supply circuit PU2. If the time is earlier, diode 041 becomes forward biased first, and the potential of the inverting input of comparator R3Z21 becomes higher than that of the non-inverting input, so that transistor Q2. is in a four-way state, and therefore, the DC stabilized power supply circuit pu2 operates so that the anode potential of the diode D42 becomes approximately the same potential as the cathode, and no DC is supplied to the load 49. At this time, the excess/deficiency voltage detection terminal 29 of the DC converter 24 is connected to the potential of the output terminal 30 of the DC stabilized power supply circuit PU2. On the other hand, since the inverting input of the comparator Z1 is brought to a low level by the output of the comparator Z21 via the resistor lR24, it will be slightly lower than the non-inverting input if the resistance value of the resistor R23 is appropriately selected. Here, since the transistor Q1 is in a non-thin conduction state, the DC stabilized power supply circuit p
ul is the voltage value of the potential of the cathode of diode D41■
, 3, and supplies direct current to the load 49, becoming the current machine. At this time, the over/under voltage detection terminal 9 of the DC stabilizing section 4 is connected to the cathode of the diode D41, ie, the load end Vε, through the resistor R2.
次に、現用機が何らかの故障により、負荷４９に過電圧
または不足電圧を与える状態になると直流安定化部４は
これを検出し、直流安定化電圧回路ＰＵＩの電源出力を
停止させる。これによりダイオードＤ４１のアノード電
位は急速に降下するが、ダイオ−ＦＤ４１のカソード電
位はコンデンサｃｌの蓄積する電荷の影響で徐々に降下
する。したがって比較器Ｚ２１の反転入力電位が非反転
入力電位より低くなり、比較器Ｚ２１の出力がハイレベ
ルになり、またトランジスタＱ２１は非導通状態になり
、直流安定化電源回路ＰＵ２はダイオードＤ４１のカソ
ードの電位が■３となるように動作を開始して、負荷４
９に直流供給を行うともに、直流安定化部２４の過不足
電圧検出端子２９は抵抗器Ｒ２１を介して、ダイオード
Ｄ４２のカソードすなわち負荷端に接続される。Next, when the current machine is in a state where overvoltage or undervoltage is applied to the load 49 due to some kind of failure, the DC stabilizing section 4 detects this and stops the power output of the DC stabilizing voltage circuit PUI. As a result, the anode potential of the diode D41 drops rapidly, but the cathode potential of the diode FD41 gradually drops due to the influence of the charge accumulated in the capacitor cl. Therefore, the inverting input potential of the comparator Z21 becomes lower than the non-inverting input potential, the output of the comparator Z21 becomes high level, the transistor Q21 becomes non-conducting, and the DC stabilizing power supply circuit PU2 changes the voltage at the cathode of the diode D41. Start operation so that the potential becomes ■3, and load 4
9, and the over/under voltage detection terminal 29 of the DC stabilizing section 24 is connected to the cathode of the diode D42, that is, the load end, via the resistor R21.
以上説明したように、コンデンサＣ４１、抵抗器ＲＩ
Ｒ２、Ｒ３、Ｒ４、Ｒ２１、Ｒ，２２、Ｒ２３およびＲ
２４の値を適切に選ぶことにより、負荷４９に対する現
用機から予備機への切換え時の過渡現象を抑制するとと
もに、過不足電圧検出が現用機では負荷端で行われ、ま
た予ＯＭＩｍではその出力端で行子４２または端子３１
と端子４３の間の接続が外れた場合でも比軸器Ｚｌまた
はＺ２１の非反転入力を低レベルにし、かつトランジス
タＱ１またはＣ２１を導通状態にして直流安定化電源回
路ＰＵＩまたはＰＵ２の出力電圧の異常上昇を阻止する
もので抵抗器Ｒ２およびＲ２２の抵抗値は抵抗器Ｒ１お
よびＲ２１の抵抗値よりも十分に大きく設定される。As explained above, capacitor C41, resistor RI
R2, R3, R4, R21, R, 22, R23 and R
By appropriately selecting the value of 24, transient phenomena at the time of switching from the working machine to the standby machine for the load 49 can be suppressed, and over/under voltage detection is performed at the load end in the working machine, and its output in the preliminary OMIm. At the end, line 42 or terminal 31
Even if connection between The resistance values of resistors R2 and R22 are set to be sufficiently larger than the resistance values of resistors R1 and R21.
この実施例装置ではトランジスタＱ１およびＣ２１にＰ
ＮＰ形トランジスタを用いているが非安定化電源ｌの端
子２および２１の端子２２が接地される場合にはＮＰＮ
形トランジスタを用いても本発明を実施することができ
る。In this embodiment device, transistors Q1 and C21 have P
Although an NP type transistor is used, if terminals 2 and 22 of the unregulated power supply l are grounded, an NPN transistor is used.
The present invention can also be practiced using type transistors.
本発明は、以上説明したように、現用・予備切換時の負
荷に対する過渡変動を抑圧し、現用・予備のそれぞれの
直流安定化電源回路の出力電圧を正しく監視することが
できるので電源異常時の負荷への影響を最少限に止める
効果がある。As explained above, the present invention suppresses transient fluctuations in the load during switching between the working and standby DC power supply circuits, and can correctly monitor the output voltages of the working and standby DC stabilized power supply circuits. This has the effect of minimizing the impact on the load.
第１図は本発明実施例装置の構成を示す接続図。
第２図は従来例装置の構成を示す接続図。
Ｃ４１・・・コンデンサ、Ｄ４１、Ｄ４２・・・ダイオ
ード、ＤＵＩ・・・ダイオードオア回路、ＰＵｌ、ＰＵ
２・・・直流安定化電源回路、Ｑｌ、Ｃ２１・・・ＰＮ
Ｐトランジスタ、Ｒ１−Ｒ５、Ｒ２１〜Ｒ２５・・・抵
抗器、Ｚｌ、Ｚ２１・・・比較器、１．２１・・・非安
定化電源、２．３．５〜１４．２２．２３．２５〜３４
．４１〜４８・・・端子、４．２４・・・直流安定化部
、１５．３５・・・切換制御部、４９・・・負荷。FIG. 1 is a connection diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a connection diagram showing the configuration of a conventional device. C41...Capacitor, D41, D42...Diode, DUI...Diode OR circuit, PUl, PU
2...DC stabilized power supply circuit, Ql, C21...PN
P transistor, R1-R5, R21-R25...Resistor, Zl, Z21...Comparator, 1.21...Unregulated power supply, 2.3.5-14.22.23.25- 34
．． 41-48...Terminal, 4.24...DC stabilizing section, 15.35...Switching control section, 49...Load.
Claims (1)
源回路を備え、 その二つの直流安定化電源回路にはそれぞれ、外部直流
電源の非接地側の端子に接続された入力端子と、 この外部直流電源の接地側の端子および外部負荷の接地
側の端子に接続された接地端子と、出力端子と、 過電圧および不足電圧を検出する第一の検出端子と、 安定化電圧を検出する第二の検出端子と を含み、 上記各出力端子と、上記外部負荷の非接地側の端子との
間にそれぞれ出力電流の方向に順方向に接続されたダイ
オード を備えた電源切換装置において、 上記二つの直流安定化電源回路には、それぞれ、上記第
一の検出端子と上記第二の検出端子とがそのコレクタに
接続され、上記出力端子にそのエミッタが接続されたト
ランジスタと、 このトランジスタのコレクタと上記接地端子との間に挿
入され、直列接続された第一の抵抗器および第二の抵抗
器と、 上記出力端子にその一端が接続された第三の抵抗器と、 上記トランジスタのベースにその一端が接続された第五
の抵抗器と、 この第五の抵抗器の他端と上記第三の抵抗器の他端との
間に挿入された第四の抵抗器と、 上記第一の抵抗器と上記第二の抵抗器との接続点がその
非反転入力に接続され、その出力が上記第四の抵抗器と
上記第五の抵抗器の接続点に接続された比較器と を備え、 一方の直流安定化電源回路の比較器の反転入力が他方の
直流安定化電源回路の第三の抵抗器と第四の抵抗器との
接続点に接続され、 また、上記第一の抵抗器と上記第二の抵抗器の接続点が
上記負荷端子の他方の端子に接続されたことを特徴とす
る電源切換装置。(1) Equipped with two DC stabilized power supply circuits each including a DC stabilization section, and each of the two DC stabilized power supply circuits has an input terminal connected to the non-grounded side terminal of the external DC power supply. A grounding terminal connected to the grounding terminal of the external DC power supply and the grounding terminal of the external load, an output terminal, a first detection terminal for detecting overvoltage and undervoltage, and a second detection terminal for detecting stabilized voltage. A power supply switching device comprising a detection terminal and a diode connected forward in the direction of the output current between each of the output terminals and the non-grounded terminal of the external load. The DC stabilized power supply circuit includes a transistor whose collector is connected to the first detection terminal and the second detection terminal, and whose emitter is connected to the output terminal, and the collector of this transistor and the above-mentioned transistor. a first resistor and a second resistor that are inserted between the ground terminal and connected in series; a third resistor that has one end connected to the output terminal; and one end of the resistor that is connected to the base of the transistor. a fourth resistor inserted between the other end of the fifth resistor and the other end of the third resistor, and the first resistor and a comparator whose output is connected to the connection point of the fourth resistor and the fifth resistor; The inverting input of the comparator of the DC stabilized power supply circuit is connected to the connection point between the third resistor and the fourth resistor of the other DC stabilized power supply circuit, and the first resistor and the A power switching device characterized in that a connection point of the second resistor is connected to the other terminal of the load terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169053A JPS6149619A (en) | 1984-08-13 | 1984-08-13 | Power source switching device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59169053A JPS6149619A (en) | 1984-08-13 | 1984-08-13 | Power source switching device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6149619A true JPS6149619A (en) | 1986-03-11 |
| JPH0524734B2 JPH0524734B2 (en) | 1993-04-08 |
Family
ID=15879457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59169053A Granted JPS6149619A (en) | 1984-08-13 | 1984-08-13 | Power source switching device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6149619A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0468443U (en) * | 1990-10-22 | 1992-06-17 |
-
1984
- 1984-08-13 JP JP59169053A patent/JPS6149619A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0468443U (en) * | 1990-10-22 | 1992-06-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0524734B2 (en) | 1993-04-08 |
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