JPS6155253U

JPS6155253U -

Info

Publication number: JPS6155253U
Application number: JP14041484U
Authority: JP
Priority date: 1984-09-18
Filing date: 1984-09-18
Publication date: 1986-04-14

Description

[Brief explanation of the drawing]

第１図は本考案の特徴を最もよく表わす図、第
２図および第３図は本考案になるノイズリダクシ
ヨン回路の第１および第２実施例を示すブロツク
系統図、第４図は第２図および第３図に示したノ
イズリダクシヨン回路の各構成部分の入出力波形
を示す図、第５図および第６図は従来のノイズリ
ダクシヨン回路のブロツク系統図、第７図は従来
のノイズリダクシヨン回路の各構成部分の出力を
示す図であり、同図Ａは減算器３の出力、同図Ｂ
所定のリミツタレベルを越えた信号成分およびこ
の信号成分に含まれるノイズ成分がカツトされて
いる減衰器６の出力、をそれぞれ示す図である。２…１Ｈ遅延回路、３，１４…減算器、８…リ
ミツタ、９，１０…第１および第２のスライサ、
１１，１２，１３…第１、第２、第３の減衰器。 FIG. 1 is a diagram that best represents the features of the present invention, FIGS. 2 and 3 are block system diagrams showing the first and second embodiments of the noise reduction circuit of the present invention, and FIG. Figures 5 and 6 are block diagrams of conventional noise reduction circuits, and Figure 7 shows conventional noise reduction circuits. 3 is a diagram showing the output of each component of the reduction circuit, in which A is the output of the subtracter 3, B is the output of the subtracter 3;
FIG. 6 is a diagram showing a signal component exceeding a predetermined limiter level and an output of the attenuator 6 from which noise components contained in this signal component are cut. 2... 1H delay circuit, 3, 14... Subtractor, 8... Limiter, 9, 10... First and second slicer,
11, 12, 13...first, second, and third attenuators.

Claims

[Claims for Utility Model Registration] (1) A delay circuit that adds a delay time of one horizontal scanning period to an input signal, and a first subtracter that subtracts the output signal of the delay circuit from the input video signal containing noise. a limiter for limiting the amplitude of the output signal of the first subtracter; a first slicer for extracting noise in the signal component exceeding the upper limit of the limiter level of the limiter; a second slicer for removing noise in a signal component exceeding a lower limit; a first attenuator for attenuating the output signal level of the limiter; and attenuating the output signal level of the first slicer. a second attenuator for attenuating the output signal level of the second slicer, and subtracting the output signals of the first to third attenuators from the input video signal. and a second subtracter. (2) The utility model according to claim (1), characterized in that the input signal supplied to the delay circuit is an input video signal containing noise, which is supplied to the first subtracter. Noise reduction circuit. (3) The noise reduction circuit according to claim (1), wherein the input signal supplied to the delay circuit is the output signal of the second subtracter.