JPS6155337U - - Google Patents

Info

Publication number
JPS6155337U
JPS6155337U JP1984140602U JP14060284U JPS6155337U JP S6155337 U JPS6155337 U JP S6155337U JP 1984140602 U JP1984140602 U JP 1984140602U JP 14060284 U JP14060284 U JP 14060284U JP S6155337 U JPS6155337 U JP S6155337U
Authority
JP
Japan
Prior art keywords
hole
integrated circuit
substrate
resin
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984140602U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984140602U priority Critical patent/JPS6155337U/ja
Publication of JPS6155337U publication Critical patent/JPS6155337U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａは本考案の一実施例の製造途中の仮基
板除去前の断面図、同図ｂは仮基板除去後の断面
図、第２図は従来の薄形化集積回路装置の断面図
である。 １…プリント配線基板、２…貫通穴、３…集積
回路素子、４…集積回路素子固着樹脂、５…導電
端子、６…金属細線、７…枠、８…封止エポキシ
樹脂、９…仮基板。 FIG. 1a is a cross-sectional view of an embodiment of the present invention before the temporary substrate is removed during manufacture, FIG. 1b is a cross-sectional view after the temporary substrate is removed, and FIG. 2 is a cross-sectional view of a conventional thinned integrated circuit device. It is. DESCRIPTION OF SYMBOLS 1... Printed wiring board, 2... Through hole, 3... Integrated circuit element, 4... Integrated circuit element fixing resin, 5... Conductive terminal, 6... Metal thin wire, 7... Frame, 8... Sealing epoxy resin, 9... Temporary board .

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板の表面から裏面に貫通する穴をあけ、
この穴の裏面開口を塞いで仮基板を設け、前記穴
の中の前記基板面に集積回路素子を樹脂でもつて
固着し、この集積回路素子の電極パツドと前記絶
縁基板上の導電端子との間を金属細線で接続し、
つぎに、前記穴の中の集積回路素子を前記固着樹
脂と同じ樹脂で包覆し、それから前記仮基板を取
り除いてなることを特徴とする集積回路装置。 Drill a hole through the insulating board from the front side to the back side,
A temporary substrate is provided by closing the back opening of this hole, and an integrated circuit element is fixed with resin to the surface of the substrate in the hole, and between the electrode pad of this integrated circuit element and the conductive terminal on the insulating substrate. Connect with thin metal wire,
Next, the integrated circuit device in the hole is covered with the same resin as the fixing resin, and then the temporary substrate is removed.
JP1984140602U 1984-09-17 1984-09-17 Pending JPS6155337U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984140602U JPS6155337U (en) 1984-09-17 1984-09-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984140602U JPS6155337U (en) 1984-09-17 1984-09-17

Publications (1)

Publication Number Publication Date
JPS6155337U true JPS6155337U (en) 1986-04-14

Family

ID=30698956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984140602U Pending JPS6155337U (en) 1984-09-17 1984-09-17

Country Status (1)

Country Link
JP (1) JPS6155337U (en)

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