JPS6155774B2 - - Google Patents
Info
- Publication number
- JPS6155774B2 JPS6155774B2 JP54133431A JP13343179A JPS6155774B2 JP S6155774 B2 JPS6155774 B2 JP S6155774B2 JP 54133431 A JP54133431 A JP 54133431A JP 13343179 A JP13343179 A JP 13343179A JP S6155774 B2 JPS6155774 B2 JP S6155774B2
- Authority
- JP
- Japan
- Prior art keywords
- tin
- gold
- thermal fatigue
- semiconductor device
- weight
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、耐熱疲労特性に優れた半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having excellent thermal fatigue resistance.
一般に、例えばパワートランジスタ等の半導体
装置は、素子配設基台上に半田等のろう材を載置
し、このろう材を介して半導体素子を接合すると
ともに、その接合部を電極として兼用した構造を
有している。 In general, semiconductor devices such as power transistors have a structure in which a brazing material such as solder is placed on an element mounting base, and the semiconductor elements are bonded via this brazing material, and the bonded portion is also used as an electrode. have.
而して、従来半導体素子と素子配設基台との接
合に用いられるろう材としては、金共晶を主成分
とする金―錫、金―シリコン系と鉛を主成分とす
る鉛―錫系、および錫を主成分とする錫系半田が
用いられている。 Conventionally, the brazing materials used for bonding semiconductor elements and element mounting bases are gold-tin, gold-silicon, which has gold eutectic as its main component, and lead-tin, which has lead as its main component. and tin-based solder whose main component is tin.
しかしながら、ろう材として金共晶を主成分と
した金（80重量％）―錫（20％）系、金―シリコ
ン（3.5重量％）を用いるものでは、接着後の熱
疲労特性が優れているが、金の含有量が多い為に
非常に高価であり経済性が悪い。また、半導体素
子の形状が大きくなると半導体素子と素子配設基
台との熱膨張係数の差異により、熱衝撃試験（−
45℃〜150℃の温度範囲における）の際に半導体
素子が破損し易い欠点がある。 However, those that use gold (80% by weight)-tin (20%) based on gold eutectic as the main component and gold-silicon (3.5% by weight) as brazing materials have excellent thermal fatigue properties after bonding. However, due to its high gold content, it is very expensive and uneconomical. In addition, as the shape of the semiconductor element becomes larger, thermal shock tests (-
There is a drawback that the semiconductor element is easily damaged in the temperature range of 45°C to 150°C.
一方、鉛を主成分とする鉛―錫系半田や錫を主
成分とする錫―銀半田は、半田が軟かい為に熱衝
撃試験での素子の破損はないが、熱疲労時に半田
が酸化し易く熱疲労特性の劣化が大きい欠点があ
る。 On the other hand, lead-tin solder containing lead as the main component and tin-silver solder containing tin as the main component do not cause element damage in thermal shock tests because the solder is soft, but the solder oxidizes during thermal fatigue. It has the disadvantage of being easy to bend and causing a large deterioration of thermal fatigue properties.
本発明は、かかる点に鑑みてなされたものであ
り、熱衝撃による半導体素子の破損がなくしかも
熱疲労特性に優れた半導体装置を提供するもので
ある。 The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device that does not cause damage to semiconductor elements due to thermal shock and has excellent thermal fatigue characteristics.
以下、本発明の実施例について説明する。 Examples of the present invention will be described below.
第１図Ａ及び同図Ｂは、本発明に係る半導体装
置の一実施例の構成を示す説明図である。図中１
は、素子配設基台２の主面にニツケルメツキ層３
を介して被着されたろう層である。ろう層１は、
素子配設基台２に半導体素子４を接合する錫―イ
ンジウムからなるろう材５と、半導体素子４の下
面に電極として形成されたニツケルメツキ層３に
酸化防止のために施された金メツキ６とが合金化
して形成されたものである。 FIGS. 1A and 1B are explanatory diagrams showing the structure of an embodiment of a semiconductor device according to the present invention. 1 in the diagram
is a nickel plating layer 3 on the main surface of the element mounting base 2.
The solder layer is applied through the solder layer. The wax layer 1 is
A brazing material 5 made of tin-indium that joins the semiconductor element 4 to the element mounting base 2, and a gold plating 6 applied to the nickel plating layer 3 formed as an electrode on the lower surface of the semiconductor element 4 to prevent oxidation. It is formed by alloying.
ここで、ろう層１を形成するろう材に錫を主成
分としてインジウムを含有したものを用いた理由
は、科学理論によつて十分に解明されていないが
この組成によつて熱疲労試験中に発生し易いクラ
ツクの発生を抑えられることが実験的に確認され
ていることに基づく。 The reason why a filler metal containing tin and indium as the main component for forming the filler layer 1 is not fully elucidated by scientific theory, but this composition makes it possible to This is based on the fact that it has been experimentally confirmed that the occurrence of cracks that are likely to occur can be suppressed.
また、ろう層１に含有されるインジウムの量
は、7.5重量％〜9.5重量％の範囲であることが望
ましい。その理由は、インジウムの量が9.5重量
％以上になると急激に融点（固相線）が下がり不
安定であるだけでなくトランジスタの保証温度
（ケース温度で150℃）が保証できなくなり、7.5
重量％以下になると錫の組織をもつことになり、
ろう層１の熱疲労特性が悪くなるからである。 Further, the amount of indium contained in the brazing layer 1 is preferably in the range of 7.5% by weight to 9.5% by weight. The reason for this is that when the amount of indium exceeds 9.5% by weight, not only does the melting point (solidus line) suddenly drop and become unstable, but the guaranteed temperature of the transistor (case temperature of 150°C) cannot be guaranteed.
If it is less than % by weight, it will have a tin structure,
This is because the thermal fatigue properties of the brazing layer 1 become worse.
また、ろう層１中に含有される金、銀、ニツケ
ル、銅の量は、２重量％以下であることが望まし
い。その理由は、２重量％を越えるとこれらの金
属と錫との合金が形成されろう層１に亀裂が発生
し易くなり熱疲労特性が著しく劣化するからであ
る。 Further, the amount of gold, silver, nickel, and copper contained in the brazing layer 1 is preferably 2% by weight or less. The reason for this is that if the content exceeds 2% by weight, an alloy of these metals and tin is formed, making it easy for cracks to occur in the braze layer 1, resulting in a significant deterioration of thermal fatigue properties.
而して、この半導体装置７は、主面にニツケル
メツキ層３を形成した素子配設基台２錫―インジ
ウムからなるろう材５を圧接した後、更にこれを
加熱溶融してその上に、下面に金メツキ６を施し
たニツケルメツキ層３を有する半導体素子４を接
合することにより作製される。 In this way, this semiconductor device 7 is constructed by press-welding a brazing material 5 made of tin-indium to an element mounting base 2 having a nickel plating layer 3 formed on its main surface, and then heating and melting the soldering material 5 to form a nickel plating layer 3 on the bottom surface. It is manufactured by bonding a semiconductor element 4 having a nickel plating layer 3 on which a gold plating 6 is applied.
このように構成された半導体装置７の熱抵抗を
熱疲労サイクル数０〜10000の範囲で測定して熱
疲労試験を行つたところ第２図Ａに示す結果を得
た。これと比較するために鉛―錫系半田或は錫―
銀系半田で形成されたろう層を有する従来の半導
体装置の熱疲労試験を上記と同様の条件で行つた
ところ同図Ｂに示す結果を得た。 When a thermal fatigue test was conducted by measuring the thermal resistance of the semiconductor device 7 constructed in this way over a range of thermal fatigue cycles from 0 to 10,000, the results shown in FIG. 2A were obtained. For comparison, lead-tin solder or tin-
A thermal fatigue test of a conventional semiconductor device having a solder layer made of silver-based solder was conducted under the same conditions as above, and the results shown in Figure B were obtained.
第２図Ａ及び同図Ｂに示す結果から明らかな如
く、実施例の半導体装置７は、従来の半導体装置
に比べて熱疲労サイクル数が10000のところで
１／４〜１／５の熱抵抗を示し格段に熱疲労特性
が改善されていることが判つた。また、熱衝撃試
験においても実施例の半導体装置７では半導体素
子４の破損は見られなかつたが、比較した従来の
ものでは半導体素子の破損が発生し使用不能とな
つた。 As is clear from the results shown in FIGS. 2A and 2B, the semiconductor device 7 of the example has a thermal resistance of 1/4 to 1/5 at 10,000 thermal fatigue cycles compared to the conventional semiconductor device. It was found that the thermal fatigue properties were significantly improved. Furthermore, in the thermal shock test, no damage to the semiconductor element 4 was observed in the semiconductor device 7 of Example, but in the conventional device for comparison, the semiconductor element was damaged and became unusable.
以上説明した如く、本発明に係る半導体装置
は、ろう層を主成分が錫とし、かつ、7.5〜9.5重
量％のインジウム及び金、銀、ニツケル、銅の少
なくとも１つを２重量％以下含有したもので形成
したので、熱疲労特性及び耐熱衝撃性に優れると
ともに、価格的にも金共晶を主成分とするろう層
を有する半導体装置に比べて非常に安価である等
顕著な効果を有するものである。 As explained above, the semiconductor device according to the present invention has a brazing layer mainly containing tin and containing 7.5 to 9.5% by weight of indium and 2% by weight or less of at least one of gold, silver, nickel, and copper. Because it is made of metal, it has excellent thermal fatigue properties and thermal shock resistance, and it also has remarkable effects such as being much cheaper than semiconductor devices that have a solder layer whose main component is gold eutectic. It is.
第１図Ａ及び同図Ｂは、本発明の一実施例の構
成を示す説明図、第２図Ａは、同実施例の熱疲労
特性を示す特性図、同図Ｂは、従来の半導体装置
の熱疲労特性を示す特性図である。
１…ろう層、２…素子配設基台、４…半導体素
子、７…半導体装置。
1A and 1B are explanatory diagrams showing the configuration of an embodiment of the present invention, FIG. 2A is a characteristic diagram showing the thermal fatigue characteristics of the embodiment, and FIG. 2B is a diagram of a conventional semiconductor device. FIG. 3 is a characteristic diagram showing the thermal fatigue characteristics of DESCRIPTION OF SYMBOLS 1... Brazing layer, 2... Element arrangement base, 4... Semiconductor element, 7... Semiconductor device.
Claims (1)
量％のインジウムを含有し、かつ、金、銀、ニツ
ケル、銅の少なくとも１つを２重量％以下含有す
るろう層を介して素子配設基台に接合されている
ことを特徴とする半導体装置。1. The semiconductor element is made of tin as a main component, contains 7.5 to 9.5% by weight of indium, and contains at least 2% by weight of at least one of gold, silver, nickel, and copper. A semiconductor device characterized by being bonded to a base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13343179A JPS5656644A (en) | 1979-10-16 | 1979-10-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13343179A JPS5656644A (en) | 1979-10-16 | 1979-10-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5656644A JPS5656644A (en) | 1981-05-18 |
| JPS6155774B2 true JPS6155774B2 (en) | 1986-11-29 |
Family
ID=15104607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13343179A Granted JPS5656644A (en) | 1979-10-16 | 1979-10-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5656644A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342442B1 (en) * | 1998-11-20 | 2002-01-29 | Agere Systems Guardian Corp. | Kinetically controlled solder bonding |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5729047A (en) * | 1980-07-29 | 1982-02-16 | Oodoko Seisakusho:Kk | Device for operating photosensitive plate holder of photocomposer |
-
1979
- 1979-10-16 JP JP13343179A patent/JPS5656644A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5656644A (en) | 1981-05-18 |
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