JPS6161396B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a rhythm generating device that has a simplified configuration by reducing the envelope coefficient memory that stores envelope information. In the past, several proposals have already been made regarding rhythm generation circuits and the like that generate multiple sound sources using sound source addition coefficients and attack decay coefficients. This rhythm generation circuit consists of a sound source section that generates a sound source frequency based on rhythm selection, and an envelope section that gives an envelope waveform to this.Sound source addition coefficients and attack decay coefficients are stored in respective memories, and an accumulator for each coefficient is used. A desired rhythm sound is generated by generating various sound source waveforms or envelope waveforms and performing multiplication with a predetermined combination. FIG. 1 is an explanatory diagram of the configuration of one example of this rhythm generating circuit. In this case, if the number of sound sources is 16, then 16
channel is required. Then, the envelope waveform and sound source waveform are formed in a time-division manner.
A rhythm sound corresponding to the selected rhythm pattern signal is output. In the same figure, attack signal A of rhythm pattern signals (hereinafter referred to as attack signals) A and B is input to an envelope control circuit 17, and attack and decay timings of the envelope waveform are formed by signals C1 and C2, which will be described later.
The channel designation signal CH1 from the channel decoder 21 designated through the address counter 20 driven by the timing generation circuit 19 is given to the envelope control circuit 17, and the designated address signal is sent to the envelope coefficient memory 13 through the OR circuit 15. input. Envelope coefficient memory 13
is determined by the address from the address counter 20,
The attack and decay addition coefficients described below are read out, and the adder, gate circuit, register, and memory circuit (RAM) are read out through the on-controlled coefficient gate 26.
is applied to an accumulator 11 consisting of: Next, the attack signal B is input to the envelope control circuit 18, and similarly to the envelope control circuit 17, the attack and decay timings of the envelope waveform are controlled by the signals C1 and C.
2, the channel designation signal CH16 from the channel decoder 21 is given to the envelope control circuit 18, and the designated address signal is ORed.
It is input to the envelope coefficient memory 13 via the circuit 15. In this case, the coefficient gate 26 is the accumulator 11
When the attack end signal C1 is generated from the envelope control circuit 18, the control signal obtained through the envelope control circuit 18 becomes "H", so that the control signal is turned off and other numbers given from the envelope coefficient memory 13 to the accumulator 11 are cut off. do. As a result, the accumulator 11 is “0”
, the same value will be held and output will continue. That is, envelope control circuit 1
7 and 18, the on/off state of the coefficient gate 26 is changed when the attack end signal C1 from the accumulator 11 is generated, thereby selecting an envelope without a hold state or an envelope with a hold state. In this circuit, both types of waveforms are included in the designated channel. In the accumulator 11, an address counter 20
and the envelope control circuit 17,
18 through the OR circuit 16, the addition coefficients are accumulated, and 8-bit binary address information is output as an accumulated output signal, which is applied to the envelope waveform table 14. The processing data of the accumulator 11 is 10 bits, and carry signals C1 and C2 are included in addition to the 8-bit address data. When 8-bit address data is sent to the envelope waveform table 14, the upper 5 bits are used as the address, and the lower 3 bits are truncated. Further, the signal C1 indicates that the attack period has ended, and the signal C2 indicates that the decay has ended, and is sent to the envelope control circuit 17 described above. In this accumulator 11, accumulated output signals of 16 envelope waves corresponding to 16 channels are obtained. Next, the contents of the envelope waveform table 14 are input into the exclusive (EX) OR circuit 22, and when the signal C1 becomes higher level than the initial value of the next cycle after the completion of 32 words of the attack waveform by the signal C1, the contents of the envelope waveform table 14 are input. The data is inverted to form a decay waveform. This EX-OR circuit 22
An envelope waveform is obtained by converting the output into an analog quantity through the D/A converter 23. The sound source section has the same configuration as the envelope section,
The sound source addition coefficient is read out from the tone coefficient memory 30 in synchronization with the channel address from the address counter 20, and the adder, gate circuit, register,
The signal is applied to a tone accumulator 31 consisting of a memory circuit (RAM). The tone coefficients here are accumulated, and a half-wavelength sine wave is output from the 256-word sine wave table 32 using the accumulated output signal corresponding to the sound source frequency as an address. This output is input to the EX-OR circuit 33 as in the case of the envelope, and is inverted by the carry signal C1' of the accumulated output signal of the tone accumulator 31 to obtain a digital sine wave sound source waveform. The frequency of this sound source waveform is input to the multiplication type D/A converter 34, and is converted into an analog signal multiplied by the envelope waveform from the D/A converter 23 of the above-mentioned envelope section. Then, the analog multiplexer 35 divides the time-divided analog data into channels CH1 to CH16, and the sample and hold circuit 36 holds and outputs the analog data of 1/16 unit time. As a method for simplifying the above-mentioned configuration, as proposed by the present applicant in a separate application and shown in an embodiment described later, frequency information and envelope information are divided and accumulated in a time-division manner using a common accumulator. By doing so, it was possible to effectively reduce the size. As another method, in the previously proposed envelope coefficient memory, the attack coefficient part and the decay coefficient part were stored in separate addresses, but the present inventor focused on the fact that both can be stored in the same address, and developed this method. The idea was to reduce the capacity by half by switching it externally. SUMMARY OF THE INVENTION An object of the present invention is to provide a rhythm generating device that has a simplified and compact envelope coefficient memory that stores envelope information. In order to achieve the above object, the rhythm generating device of the present invention stores frequency information in a tone coefficient memory and accumulates the information to read musical tones from a musical waveform memory, and a musical tone generating circuit that reads musical tones from a musical waveform memory; By storing information and accumulating the information, an envelope forming circuit reads an envelope waveform from an envelope memory, and an address is specified for causing the operations of the musical tone generating circuit and the envelope forming circuit to be performed in a time-sharing manner. A rhythm generating device equipped with an address counter, characterized in that the envelope forming memory stores an attack coefficient in the upper part of the same address and a decay coefficient in the lower part, and is provided with means for switching and reading out the contents of the upper part and the lower part. That is. The present invention will be described in detail below with reference to examples. FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention. In the same figure, the address counter 20 of FIG.
Tone coefficient memory (ROM) 3 at address from
0 and envelope coefficient memory (ROM) 13. Frequency information from the tone coefficient memory 30 is passed through an AND gate 41, synchronized with time _H1 of T1 and _H2 , _which are time-divided one address interval, and passed through an OR gate 43 to a common accumulator 44 shown in broken lines.
Put it in. On the other hand, the configuration of the envelope coefficient memory 13, which is the main part of the present invention, is as described in detail later.
The attack coefficient is stored in the upper bits of the address data, and the decay coefficient is stored in the lower bits.
This readout output is connected to an AND gate 45,
into the AND gate 46, and the inverter 47 into the latter
The attack and decay control signals are applied and switched by the control line inserted, and the output is synchronized with the _T2 time described above and the envelope and zero cross control signals described later, and the output is sent to the common accumulator 44 via the OR gate 43. Put it in. The accumulator 44 has a loop consisting of a full adder 51 as a tone accumulator, a tone register 52, and a tone storage circuit (RAM) 53, with the full adder 51 in common, and a full adder 51 as an envelope accumulator. It consists of a loop consisting of an AND gate 54, an envelope register 55, and an envelope storage circuit (RAM) 56. The contents of the envelope coefficients are switched into attack coefficients and decay coefficients by the attack and decay control signals as described above. In the tone accumulator loop, the time data of _T1 from the tone coefficient memory 30 is ORed with the AND gate 41.
The data is input to the full adder 51 via the gate 43, and at the same time, the previous data from the tone storage circuit 53 is read out to the full adder 51 and added.
This content is stored in the tone storage circuit 53, and is also sent to the sine wave table 32, where a half-wavelength sine wave is read out and sent to the D/A converter 34 according to the procedure shown in FIG. In the envelope accumulator loop, the time data of T ₂ from the envelope coefficient memory 13 are ANDed.
Full adder 5 via gate 42 and OR gate 43
1 and simultaneously read out the previous data from the envelope storage circuit 56 to the full adder 51 and add it, gated by the AND gate 54 with the control signal from the envelope controller explained in FIG.
It is latched into the envelope register 55, and its contents are stored in the envelope storage circuit 56 and sent to the envelope waveform table 14.
The envelope waveform is read out and sent to the D/A converter 23 according to the procedure shown in FIG. FIG. 3 shows a detailed circuit example of the main part of the present invention in the embodiment shown in FIG. In the figure, tone coefficient memory 30 and envelope coefficient memory 13 are accessed in parallel by a 6-bit address from address counter 20, for example. For example, 10-bit frequency data read from tone coefficient memory 30 is sent to full adder 51 via OR gate 43 in synchronization with time _T1 by AND gate 41. On the other hand, in the envelope coefficient memory 13, the attack coefficient is stored in the upper three bits of one word read out at one address, and the decay coefficient is stored in the lower six bits. In an envelope waveform, attack generally has a steep rise, and decay has a slow fall. Therefore, the attack coefficients are mostly concentrated at the top of each rhythm, and the decay coefficients are concentrated at the bottom. Utilizing this characteristic, it is possible to store attack coefficients in the upper part and decay coefficients in the lower part of the same address. The following table shows an example of attack and decay bits for each rhythm. Then, the top 3 bits corresponding to the attack are
AND gate 45, lower 6 corresponding to Decay
The bit is input to AND gate 46 and sent to full adder 51 via OR gate 43 in synchronization with time _T2 . Also, this

[Table] During T ₂ hours, the attack and decay control lines are input directly to the AND gate 45 and to the AND gate 46 via the inverter 46 to control switching between attack and decay. In addition, the special request was made in 1974.
As proposed by No. 31410, to reduce multiplication distortion and noise between tone and envelope waveform,
The envelope and zero cross control signals are input to the AND gate 46 to perform synchronization. Although the embodiment shows a case where a common accumulator is used for tone and envelope, the present invention can be similarly applied to a case where separate accumulators are used as shown in FIG. As explained above, according to the present invention, the attack coefficient is stored in the upper part and the decay coefficient is stored in the lower part in the word of the same address of the envelope coefficient memory that stores envelope information, and the required coefficients are switched externally. Memory capacity can be halved. This has a large effect on downsizing the device without affecting the actual function of envelope waveform formation.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conventional proposed example, Fig. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is a detailed explanatory diagram of the main part of Fig. 2. In the figure, 13 is an envelope. Coefficient memory, 14 is an envelope waveform table, 20 is an address counter, 23 and 34 are D/
A converter, 30 is a tone coefficient memory, 32 is a sine wave table, 41, 45, 46 are AND gates,
43 is an OR gate, 44 is a common accumulator, 47 is an inverter, 51 is a full adder, 52 is a tone register, 53 is a tone storage circuit, 55 is an envelope register, and 56 is an envelope storage circuit.

Claims (1)

[Claims] 1. A musical tone generation circuit that stores frequency information in a tone coefficient memory and accumulates the information to read musical tones from the musical waveform memory; stores envelope information in an envelope coefficient memory and accumulates the information. Accordingly, in a rhythm generating device that includes an envelope forming circuit that reads an envelope waveform from an envelope memory, and an address counter that specifies an address for causing the operations of the musical tone generating circuit and the envelope forming circuit to be performed in a time-sharing manner, 1. A rhythm generating device characterized in that a coefficient memory stores an attack coefficient in the upper part of the same address and a decay coefficient in the lower part, and is provided with means for switching and reading out the contents of the upper part and the lower part.