JPS6161736B2 - - Google Patents
Info
- Publication number
- JPS6161736B2 JPS6161736B2 JP18604980A JP18604980A JPS6161736B2 JP S6161736 B2 JPS6161736 B2 JP S6161736B2 JP 18604980 A JP18604980 A JP 18604980A JP 18604980 A JP18604980 A JP 18604980A JP S6161736 B2 JPS6161736 B2 JP S6161736B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- impedance
- wire
- resistor
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000003111 delayed effect Effects 0.000 claims description 2
- 102100036464 Activated RNA polymerase II transcriptional coactivator p15 Human genes 0.000 description 8
- 101000713904 Homo sapiens Activated RNA polymerase II transcriptional coactivator p15 Proteins 0.000 description 8
- 229910004444 SUB1 Inorganic materials 0.000 description 8
- 229910004438 SUB2 Inorganic materials 0.000 description 8
- 101100311330 Schizosaccharomyces pombe (strain 972 / ATCC 24843) uap56 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 101150018444 sub2 gene Proteins 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000005236 sound signal Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/03—Hybrid circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は、４線式電子交換等において２線−４
線交換を行うために用いられる差動入力形ハイブ
リツド回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a 4-wire electronic exchange, etc.
This invention relates to a differential input type hybrid circuit used for line switching.
（従来技術とその問題点）
図１は、相互通話時の通話路モデル図であり、
SUB１，SUB２は加入者電話機、HYB１，HYB
２は２線−４線変換ハイブリツド回路、ｂS1，ｂ
S2はそれぞれSUB１，SUB２のハイブリツド回路
HYB１，HYB２の不平衡による反響減衰量を示
す。従来用いられてきたハイブリツド回路を図１
のHYB１，HYB２として用いた場合、鳴音安定
度の立場からすると、反響減衰量ｂS1，ｂS2は10
〜15（dB）程度で充分であつた。しかし、最近
のPBX技術基準に規定されている側音通話当量
（7dB以上）の立場から評価すると、前記反響減
衰量は25dB程度必要とし、それ故に、充分な平
衡がとれる高性能のハイブリツド回路が要求され
る。(Prior art and its problems) Figure 1 is a communication path model diagram during mutual communication.
SUB1, SUB2 are subscriber telephones, HYB1, HYB
2 is a 2-wire-4-wire conversion hybrid circuit, b S1 , b
S2 is a hybrid circuit of SUB1 and SUB2, respectively.
This shows the amount of reverberation attenuation due to unbalance of HYB1 and HYB2. Figure 1 shows the conventionally used hybrid circuit.
When used as HYB1 and HYB2, the reverberation attenuation b S1 and b S2 are 10
~15 (dB) was sufficient. However, when evaluated from the standpoint of the sidetone speech equivalent (7 dB or more) stipulated in recent PBX technical standards, the reverberation attenuation needs to be about 25 dB, and therefore a high-performance hybrid circuit with sufficient balance is required. required.
図２は、４線式電子交換等の加入者回路におけ
る２線−４線変換を行う差動入力型抵抗ハイブリ
ツド回路の回路例である。図１の例で説明する
と、端子１−２間には、各ハイブリツド回路
HYB１又はHYB２の受話側入力、すなわち、相
手加入者（HYB１のときはSUB２，HYB２のと
きはSUB１）からの受信音声信号電圧e2が印加さ
れる。端子３−４間には２線側すなわち加入者電
話機SUB１又はSUB２が接続され、e1は電話機
SUB１又はSUB２の音声出力電圧を示してい
る。また、Z0はハイブリツド回路HYB１又は
HYB２の２線側端子から２線線路を含む電話機
SUB１又はSUB２をみたインピーダンスを示し
ている。ｎ：１はトランスTRの巻数比を示し、
端子５は相手加入者へ送出される音声信号出力端
子である。DEFは差動増幅器を示し、Ａはその
増幅度である。ＺはトランスTRの２次側からみ
たインピーダンスを示す。Z1は２線線路の終端イ
ンピーダンス、Z2は平衡をとる為の第１の平衡回
路のインピーダンス、Z3は平衡をとる為の第２の
平衡回路のインピーダンスを示す。 FIG. 2 is a circuit example of a differential input type resistor hybrid circuit that performs 2-wire to 4-wire conversion in a subscriber circuit such as a 4-wire electronic exchange. To explain using the example of Figure 1, each hybrid circuit is connected between terminals 1 and 2.
A received audio signal voltage e 2 from the receiver side input of HYB1 or HYB2, that is, the opposite subscriber (SUB2 for HYB1, SUB1 for HYB2) is applied. The 2-wire side, that is, the subscriber telephone SUB1 or SUB2 is connected between terminals 3 and 4, and e 1 is the telephone
It shows the audio output voltage of SUB1 or SUB2. Also, Z 0 is the hybrid circuit HYB1 or
A telephone that includes a 2-wire line from the 2-wire side terminal of HYB2
It shows the impedance when looking at SUB1 or SUB2. n:1 indicates the turns ratio of the transformer TR,
Terminal 5 is an audio signal output terminal to be sent to the other subscriber. DEF indicates a differential amplifier, and A is its amplification degree. Z indicates the impedance seen from the secondary side of the transformer TR. Z 1 is the terminal impedance of the two-wire line, Z 2 is the impedance of the first balancing circuit for balancing, and Z 3 is the impedance of the second balancing circuit for balancing.
図２の回路は、図３のように変換でき、図中端
子５への出力電圧Voutは次のようになる。 The circuit of FIG. 2 can be converted as shown in FIG. 3, and the output voltage Vout to the terminal 5 in the figure is as follows.
Vout＝Ａ〔〓１／〓＋〓１・ｅ１／ｎ
＋（〓／〓＋〓１−〓３／〓２＋〓３）ｅ〓２〕……
(1)
ただし、Ｚ〓＝Ｚ〓０／n2
いま、相手加入者SUB２（又はSUB１）から
到来する音声信号e2が図１に示す反響減衰量ｂS1
（又はｂS2）に基づき端子５に、回り込まない為
には上式のVout中のｅ〓２成分が０となればよい
から、
｜〓１／〓＋〓１｜＝｜〓３／〓２＋〓３｜ ……(2)
arg（〓／〓＋〓１）＝arg（〓３／〓２＋〓３）……(3
)
の２条件を満足しなければならない。以後(2)、(3)
式を平衡条件と呼ぶ。説明を簡単にする為Ｚ〓１を
純抵抗とし、Z1＝R1とする。(2)、(3)式中Ｚ〓は、
通常トランスTRのインダクタンス、加入者電話
機に至る線路のインピーダンス、電話機回路網等
により、音声帯域内の低減0.6KHz〜1KHz以下で
は誘導性であり、かつ、0.6KHz〜1KHz以上の高
域では容量性のインピーダンスをもつ。従つて、
〓１／〓＋〓１＝〓１／〓＋Ｒ１は図４の様な軌跡を描
く。Vout=A [〓 1 /〓+〓 1・e 1 /n + (〓 /〓+〓 1 −〓 3 /〓 2 +〓 3 )e〓 2 ]...
(1) However, Z〓=Z〓 0 /n 2 Now, the voice signal e 2 arriving from the other subscriber SUB2 (or SUB1) has the echo attenuation amount b S1 shown in Fig. 1.
(or b S2 ), in order to avoid looping around to terminal 5, the e〓2 component in Vout in the above formula should be 0, so |〓 1 /〓+〓 1 ｜=｜〓 3 /〓 2 +〓 3 | …(2) arg(〓/〓+〓 1 )=arg(〓 3 /〓 2 +〓 3 )……(3
) must satisfy the following two conditions. Hereafter (2), (3)
The equation is called the equilibrium condition. To simplify the explanation, let Z〓 1 be a pure resistance and Z 1 = R 1 . In formulas (2) and (3), Z〓 is
Normally, due to the inductance of the transformer TR, the impedance of the line leading to the subscriber's telephone, the telephone circuit network, etc., the reduction in the voice band is inductive in the range of 0.6KHz to 1KHz or less, and capacitive in the high range of 0.6KHz to 1KHz or higher. It has an impedance of Therefore,
〓 1 / 〓 + 〓 1 = 〓 1 / 〓 + R 1 draws a trajectory as shown in Fig. 4.
一般に、２線線路側が分布容量を持つ線路とみ
なしていたため、この様なハイブリツド回路の平
衡をとる手段として、従来抵抗とコンデンサの組
合わせあるいは、抵抗、コンデンサ及びインダク
タンスの組合わせによるインピーダンス素子が用
いられてきた。しかしながら、前記のように「２
線線路側が分布容量を持つ線路とみなす」という
前提条件のために、従来一般に行なわれていたよ
うにＺ〓２を純抵抗R2とし、Ｚ〓３を抵抗とコンデ
ンサの直列回路に別の抵抗を並列に接続した如き
組合わせにより構成した例をとると、この場合図
４の軌跡からも明らかなように、音声帯域の高域
においては平衡条件(2)、(3)両式を満足することは
可能であるが、低域においては位相が正である為
不可能である。また、Ｚ〓３の構成素子に更にイン
ダクタンスを加えた場合には、全周波数に亘り平
衡をとることは可能であるが、インダクタンスを
用いる為価格及び実装密度の点で不利である。 In general, the two-wire line side was considered to have distributed capacitance, so impedance elements such as a combination of a resistor and a capacitor, or a combination of a resistor, a capacitor, and an inductance were conventionally used as a means of balancing such hybrid circuits. I've been exposed to it. However, as mentioned above, “2
Because of the precondition that the line side is regarded as a line with distributed capacitance, Z 2 is a pure resistance R 2 and Z 3 is a series circuit of a resistor and a capacitor with another resistor, as has been commonly done. In this case, as is clear from the trajectory in Figure 4, both equilibrium conditions (2) and (3) are satisfied in the high range of the audio band Although this is possible, it is impossible in the low range because the phase is positive. Further, if an inductance is further added to the component element of Z 3 , it is possible to maintain balance over all frequencies, but since an inductance is used, it is disadvantageous in terms of cost and packaging density.
以上のように、従来の技術では全周波数に亘り
平衡をとろうとすると、前記のように、Ｚ〓２を純
抵抗R2としていたために、Ｚ〓３を抵抗及びコン
デンサの単純なインピーダンス素子だけでは実現
できなかつた。 As mentioned above, when trying to achieve balance over all frequencies with the conventional technology, since Z 2 is a pure resistance R 2 as mentioned above, Z I couldn't make it happen.
（発明の目的）
本発明は、ハイブリツドの平衡用素子をインダ
クタンスを用いずに抵抗及びコンデンサの組合わ
せとし、音声帯域の全周波数に亘り充分な平衡が
とれるように構成された差動入力形ハイブリツド
回路を構成することを目的としている。(Object of the Invention) The present invention provides a differential input type hybrid device in which the hybrid balancing element is a combination of a resistor and a capacitor without using an inductance, and is configured to achieve sufficient balance over all frequencies in the audio band. The purpose is to construct a circuit.
（発明の原理及び構成） 以下本発明を詳細に説明する。(Principle and structure of the invention) The present invention will be explained in detail below.
図３の等価回路において、２線線路の終端イン
ピーダンスＺ〓１を純抵抗R1とした場合、前記平
衡条件(3)に注目すると、第１、第２の平衡回路の
インピーダンスＺ〓２，Ｚ〓３の位相角関係が音声帯
域の低域では図５に示される関係すなわち、第１
の平衡回路のインピーダンスZ2の位相角argZ2が
第２の平衡回路のインピーダンスZ3の位相角
argZ3に対して遅れ位相となる関係にあり、高域
では図６に示される関係すなわち、前記のargZ2
が前記のargZ3に、対して進み位相となる関係に
あれば、(3)式の右辺の符号は低域高域各々におい
て、次式(4)、(5)となるから、図４に示される如き
(3)式の左辺の符号と一致させることができる。 In the equivalent circuit of FIG. 3, if the terminal impedance Z〓 1 of the two-wire line is a pure resistance R 1 , and paying attention to the equilibrium condition (3), the impedances of the first and second balanced circuits Z〓 2 , Z 〓 In the low range of the audio band, the phase angle relationship of
The phase angle of the impedance Z 2 of the balanced circuit argZ 2 is the phase angle of the impedance Z 3 of the second balanced circuit
argZ 3 has a delayed phase relationship, and in the high range, the relationship shown in FIG. 6, that is, the above argZ 2
If argZ 3 is in a leading phase with respect to argZ 3, the sign on the right side of equation (3) becomes the following equations (4) and (5) in each of the low and high ranges. as shown
It can be matched with the sign on the left side of equation (3).
これが本発明の原理である。 This is the principle of the invention.
この場合には、Ｚ〓２，Ｚ〓３の位相角は、ともに
負であるから、両者ともに抵抗及びコンデンサの
組合わせで実現でき、適当なコンデンサ及び抵抗
の値を決めることにより、平衡条件(2)、(3)の両式
を容易に満足させることができる。図７、図８は
各々本発明の原理を実現するためのＺ〓２，Ｚ〓３の
１例である。また、図９は図８を等価変換して得
られるＺ〓３の構成例である。 In this case, since the phase angles of Z〓 2 and Z〓 3 are both negative, both can be realized by a combination of a resistor and a capacitor, and by determining appropriate capacitor and resistor values, the equilibrium condition ( Both equations 2) and (3) can be easily satisfied. 7 and 8 are examples of Z〓 2 and Z〓 3 for realizing the principle of the present invention, respectively. Further, FIG. 9 is an example of the configuration of Z 3 obtained by equivalently transforming FIG. 8.
すなわち、Ｚ〓２とＺ〓３のいずれにもコンデンサ
を含む構成となつていることが、従来技術との構
成上の差異である。 That is, the difference in configuration from the prior art is that both Z 2 and Z 3 include capacitors.
0.5φ、3.5Kmの線路を用い、
｜〓１／〓＋〓１｜及びarg（〓１／〓＋〓１）
の実測値を求め、本発明の原理に従つて図７、図
８に示されるR2，R3，R′3，C1，C2を適宜に定め
たところ音声帯域内の全周波数に亘つて平衡条件
(2)、(3)をほぼ満足させることが、実験によつて明
らかになつている。 Using a 0.5φ, 3.5km line, the actual measured values of |〓 1 / 〓 + 〓 1 | By appropriately determining R 2 , R 3 , R′ 3 , C 1 , and C 2 , the equilibrium condition is reached over all frequencies within the audio band.
Experiments have revealed that (2) and (3) are almost satisfied.
以上説明した例では、Ｚ〓１を純抵抗とした場合
であるが、逆にＺ〓３を純抵抗とした場合でも、同
様な手法によつて、Ｚ〓１，Ｚ〓２を抵抗及びコンデ
ンサの組合わせによつて実現することができる。 In the example explained above, Z〓 1 is a pure resistance, but even if Z〓 3 is a pure resistance, the same method can be used to replace Z〓 1 and Z〓 2 with resistors and capacitors. This can be realized by a combination of the following.
（発明の効果）
以上説明したように、本発明は平衡用回路の構
成素子を抵抗及びコンデンサの組合わせとするこ
とにより、構成が単純かつ安価であり、しかも音
声帯域の全周波数に亘り、充分な平衡が得られる
利点がある。(Effects of the Invention) As explained above, the present invention uses a combination of resistors and capacitors as the constituent elements of the balancing circuit, so that the structure is simple and inexpensive, and moreover, the balance circuit has sufficient power over all frequencies in the audio band. This has the advantage of achieving a good balance.
図１は本発明を適用する相互通話等の通話路モ
デルを示すブロツク図、図２は本発明の差動入力
形ハイブリツド回路の基本的構成を示すブロツク
図、図３は図２の基本的構成の等価回路を示すブ
ロツク図、図４は本発明に用いる回路素子に係る
ベクトルＺ〓／Ｚ〓＋R1の軌跡特性図、図５は本発
明に用いる回路素子の低域におけるＺ〓２，Ｚ〓３の
位相角の関係を示すベクトル図、図６は本発明に
用いる回路素子の高域におけるＺ〓２，Ｚ〓３の位相
角の関係を示すベクトル図、図７は本発明に用い
る回路素子のＺ〓２の１例を示す回路図、図８は本
発明に用いる回路素子Ｚ〓３の１例を示す回路図、
図９は図８の等価変換後の回路素子Ｚ〓３の１例を
示す回路図である。
SUB１，SUB２……加入者電話機、HYB１，
HYB２……２線−４線変換ハイブリツド回路、
Z0……２線端子側をみたインピーダンス、Z1……
２線線路の終端インピーダンス、Z2……第１の平
衡回路のインピーダンス、Z3……第２の平衡回路
のインピーダンス、１，２……４線受話側端子、
３，４……２線側端子、５……４線送話側端子。
FIG. 1 is a block diagram showing a communication path model for mutual communication, etc. to which the present invention is applied, FIG. 2 is a block diagram showing the basic configuration of the differential input type hybrid circuit of the present invention, and FIG. 3 is the basic configuration of FIG. 2. FIG. 4 is a locus characteristic diagram of the vector Z〓/Z〓+R 1 related to the circuit element used in the present invention, and FIG . 〓 3 is a vector diagram showing the relationship between the phase angles of Z〓 2 and Z〓 3 in the high frequency range of the circuit element used in the present invention. Figure 7 is the circuit used in the present invention. A circuit diagram showing an example of the element Z〓 2 , FIG. 8 is a circuit diagram showing an example of the circuit element Z〓 3 used in the present invention,
FIG. 9 is a circuit diagram showing an example of the circuit element Z3 after equivalent conversion in FIG. SUB1, SUB2...Subscriber telephone, HYB1,
HYB2...2-wire to 4-wire conversion hybrid circuit,
Z 0 ... Impedance looking at the 2-wire terminal side, Z 1 ...
Terminal impedance of the two-wire line, Z 2 ... Impedance of the first balanced circuit, Z 3 ... Impedance of the second balanced circuit, 1, 2 ... 4-wire receiver side terminal,
3, 4...2-wire side terminal, 5...4-wire transmitting side terminal.
Claims (1)
第１の平衡回路がインダクタンスを用いないコン
デンサと抵抗によるインピーダンス素子によつて
構成され、該第１の平衡回路のインピーダンスの
位相角は前記一方の入力と接地間に接続される第
２の平衡回路のインピーダンスの位相角に対して
音声帯域内の低域においては遅れ位相となり高域
においては進み位相となるように設定されている
ことを特徴とする差動入力形ハイブリツド回路。1. A first balanced circuit connected in series to one input of the differential input terminal is constituted by an impedance element consisting of a capacitor and a resistor that does not use inductance, and the phase angle of the impedance of the first balanced circuit is as described above. The phase angle of the impedance of the second balanced circuit connected between one input and the ground is set so that it is a delayed phase in the low range of the audio band and a leading phase in the high range. Features a differential input type hybrid circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18604980A JPS57111133A (en) | 1980-12-27 | 1980-12-27 | Differential input type hybrid circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18604980A JPS57111133A (en) | 1980-12-27 | 1980-12-27 | Differential input type hybrid circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57111133A JPS57111133A (en) | 1982-07-10 |
| JPS6161736B2 true JPS6161736B2 (en) | 1986-12-26 |
Family
ID=16181497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18604980A Granted JPS57111133A (en) | 1980-12-27 | 1980-12-27 | Differential input type hybrid circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57111133A (en) |
-
1980
- 1980-12-27 JP JP18604980A patent/JPS57111133A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57111133A (en) | 1982-07-10 |
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