JPS61655U - information processing equipment - Google Patents
information processing equipmentInfo
- Publication number
- JPS61655U JPS61655U JP7261085U JP7261085U JPS61655U JP S61655 U JPS61655 U JP S61655U JP 7261085 U JP7261085 U JP 7261085U JP 7261085 U JP7261085 U JP 7261085U JP S61655 U JPS61655 U JP S61655U
- Authority
- JP
- Japan
- Prior art keywords
- control device
- flag information
- common bus
- setting
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を説明するブロック図、第２
図は本考案の一実施例を説明するフローチャート。
第３図は要部詳細ブロック図であり、図中に用いた符号
は次の通りである。
１は処理装置、２はメモリ、３は共通バス、４，８は制
御部、５，９はＤＭＡ制御部、６は表示部、７は文字発
生器、１０はプリンタ、７０はＣＧメモリ、７１はフラ
グレジスタ、７２はアドレスカウンタ、７３はライトコ
ントローラ、８０はプリンタコントローラ、８Ｂはフラ
グ、８Ｂ２はセレクタ、−８Ｂ３はマルチプレクサ、Ａ
はＤＭＡ要求信号、Ｂは判別部を示す。Fig. 1 is a block diagram illustrating an embodiment of the present invention;
The figure is a flowchart explaining one embodiment of the present invention. FIG. 3 is a detailed block diagram of main parts, and the symbols used in the figure are as follows. 1 is a processing unit, 2 is a memory, 3 is a common bus, 4 and 8 are control units, 5 and 9 are DMA control units, 6 is a display unit, 7 is a character generator, 10 is a printer, 70 is a CG memory, 71 is a flag register, 72 is an address counter, 73 is a write controller, 80 is a printer controller, 8B is a flag, 8B2 is a selector, -8B3 is a multiplexer, A
indicates a DMA request signal, and B indicates a determination unit.
Claims (1)
バスに結ばれ第１のフラグ情報、第２のフラグ情報及び
ＤＭＡ要求を発する処理装置と、前記共通バスに結ばれ
前記第１のフラグ情報が設定される第１の設定部及び該
第１のフラグ情報の設定を他へ通報する手段を有する第
１の制御装置と、前記共通バスに結ばれたＤＭＡ制御部
を有し前記第２のフラグ情報及びＤＭＡ要求を受けたと
き前記記憶部内のデータを自己め装置内へ転送せしめる
手段及び前謬ハ払要求を受け前記第１の制御装置から前
記第１のフラグ情報の設定済み通報を受けたとき前記記
憶部内のデータの前記第１の制御装置への転送を許容す
る通知情報を該第■の制御装置へ通報する手段を有する
第２の制御装置とを備えた情報処理装置。a common bus, a storage section connected to the common bus, a processing device connected to the common bus that issues first flag information, second flag information, and a DMA request; a first control device having a first setting section in which flag information is set; a first control device having means for notifying others of the setting of the first flag information; and a DMA control section connected to the common bus; Second flag information and a means for transferring data in the storage unit to the self-setting device upon receiving a DMA request, and setting of the first flag information from the first control device in response to a previous error compensation request. and a second control device having means for notifying the second control device of notification information that allows transfer of data in the storage unit to the first control device when a notification is received. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7261085U JPS61655U (en) | 1985-05-16 | 1985-05-16 | information processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7261085U JPS61655U (en) | 1985-05-16 | 1985-05-16 | information processing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61655U true JPS61655U (en) | 1986-01-06 |
| JPS6137085Y2 JPS6137085Y2 (en) | 1986-10-27 |
Family
ID=30611178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7261085U Granted JPS61655U (en) | 1985-05-16 | 1985-05-16 | information processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61655U (en) |
-
1985
- 1985-05-16 JP JP7261085U patent/JPS61655U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6137085Y2 (en) | 1986-10-27 |
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