JPS6168523U - - Google Patents

Info

Publication number
JPS6168523U
JPS6168523U JP15175684U JP15175684U JPS6168523U JP S6168523 U JPS6168523 U JP S6168523U JP 15175684 U JP15175684 U JP 15175684U JP 15175684 U JP15175684 U JP 15175684U JP S6168523 U JPS6168523 U JP S6168523U
Authority
JP
Japan
Prior art keywords
resistor
input terminal
differential amplifier
inverting input
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15175684U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15175684U priority Critical patent/JPS6168523U/ja
Publication of JPS6168523U publication Critical patent/JPS6168523U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Networks Using Active Elements (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例としての差動入力形
低域フイルタの回路図、第２図は第１図の低域フ
イルタを利用した波形整形回路の回路図、第３図
は従来形の差動入力形低域フイルタの回路図であ
る。 Ｑ１…差動増幅器、Ｒ１〜Ｒ７…抵抗器、Ｃ１
〜Ｃ３…キヤパシタ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１の入力端子と差動増幅器の非反転入力端子
    との間に第１の抵抗器および第２の抵抗器が直列
    接続され、該第１および第２の抵抗器の共通接続
    点が第１のキヤパシタを経て接地され、該非反転
    入力端子が第３の抵抗器を経て接地され、第２の
    入力端子と該差動増幅器の反転入力端子との間に
    第４の抵抗器および第５の抵抗器が直列接続され
    、該第４および第５の抵抗器の共通接続点が第２
    のキヤパシタを経て接地され、該差動増幅器の出
    力端子と反転入力端子の間に第６の抵抗器が接続
    された差動入力形抵域フイルタ。
JP15175684U 1984-10-09 1984-10-09 Pending JPS6168523U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15175684U JPS6168523U (ja) 1984-10-09 1984-10-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15175684U JPS6168523U (ja) 1984-10-09 1984-10-09

Publications (1)

Publication Number Publication Date
JPS6168523U true JPS6168523U (ja) 1986-05-10

Family

ID=30709853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15175684U Pending JPS6168523U (ja) 1984-10-09 1984-10-09

Country Status (1)

Country Link
JP (1) JPS6168523U (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56156053A (en) * 1980-05-02 1981-12-02 Fujitsu Ten Ltd Waveform shaping circuit
JPS5789327A (en) * 1980-11-25 1982-06-03 Fujitsu Ten Ltd Duty control type frequency multiplying circuit
JPS59149416A (ja) * 1983-02-16 1984-08-27 Hitachi Ltd 波形整形回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56156053A (en) * 1980-05-02 1981-12-02 Fujitsu Ten Ltd Waveform shaping circuit
JPS5789327A (en) * 1980-11-25 1982-06-03 Fujitsu Ten Ltd Duty control type frequency multiplying circuit
JPS59149416A (ja) * 1983-02-16 1984-08-27 Hitachi Ltd 波形整形回路

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