JPS6168566U - - Google Patents

Info

Publication number
JPS6168566U
JPS6168566U JP1984153198U JP15319884U JPS6168566U JP S6168566 U JPS6168566 U JP S6168566U JP 1984153198 U JP1984153198 U JP 1984153198U JP 15319884 U JP15319884 U JP 15319884U JP S6168566 U JPS6168566 U JP S6168566U
Authority
JP
Japan
Prior art keywords
pixel
interest
circuit
absolute value
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984153198U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984153198U priority Critical patent/JPS6168566U/ja
Priority to KR2019850009307U priority patent/KR890007509Y1/ko
Publication of JPS6168566U publication Critical patent/JPS6168566U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • H04N1/405—Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の動作を示す図、第２図は本考
案の回路を示す図。 １……文書、２……ＣＣＤセンサ・アレイ、３
……Ａ−Ｄ変換回路、４……ライン・バツフア、
５，９，１６，１６……比較回路、６……平均化
回路、７……減算回路、８……付加閾値幅設定回
路、１０……オア回路、１１，１３……選択回路
、１２……ラツチ、１４，１５……閾値発生回路
。

Claims (1)

    【実用新案登録請求の範囲】
  1. 文書上の注目画素を取囲む複数個の画素の平均
    信号レベルを上記注目画素に対する閾値として用
    いて上記注目画素の２値レベル信号を発生する回
    路と、上記注目画素及び上記閾値の差の絶対値を
    所定の値に比較し上記絶対値が上記所定の値より
    も大きい時に制御信号を発生する回路と、上記制
    御信号の存在に応答して上記注目画素の２値レベ
    ル信号を出力線にゲートし、上記制御信号の不存
    在に応答して上記注目画素に先行する画素の２値
    レベル信号を上記出力線にゲートする選択回路を
    備えたことを特徴とするイメージ処理装置。
JP1984153198U 1984-10-12 1984-10-12 Pending JPS6168566U (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1984153198U JPS6168566U (ja) 1984-10-12 1984-10-12
KR2019850009307U KR890007509Y1 (ko) 1984-10-12 1985-07-23 화상 처리장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984153198U JPS6168566U (ja) 1984-10-12 1984-10-12

Publications (1)

Publication Number Publication Date
JPS6168566U true JPS6168566U (ja) 1986-05-10

Family

ID=15557184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984153198U Pending JPS6168566U (ja) 1984-10-12 1984-10-12

Country Status (2)

Country Link
JP (1) JPS6168566U (ja)
KR (1) KR890007509Y1 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56102161A (en) * 1980-01-18 1981-08-15 Nec Corp Binary encoding circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56102161A (en) * 1980-01-18 1981-08-15 Nec Corp Binary encoding circuit

Also Published As

Publication number Publication date
KR890007509Y1 (ko) 1989-10-26
KR860005434U (ko) 1986-06-11

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