JPS6170242U - - Google Patents
Info
- Publication number
- JPS6170242U JPS6170242U JP15200384U JP15200384U JPS6170242U JP S6170242 U JPS6170242 U JP S6170242U JP 15200384 U JP15200384 U JP 15200384U JP 15200384 U JP15200384 U JP 15200384U JP S6170242 U JPS6170242 U JP S6170242U
- Authority
- JP
- Japan
- Prior art keywords
- selection signal
- operation order
- expansion
- memories
- specifying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案装置の１実施例の回路ブロツク
図、第２図は同装置の要部回路構成図である。
１…拡張メモリ受け手段（拡張スロツト）、３
…セレクト信号作成手段、８…運用順位指定手段
、９…切換回路手段。
FIG. 1 is a circuit block diagram of one embodiment of the device of the present invention, and FIG. 2 is a circuit diagram of the main part of the device. 1... Expansion memory receiving means (expansion slot), 3
...Select signal generation means, 8. Operation order designation means, 9. Switching circuit means.
Claims (1)
メモリ受け手段と、該拡張メモリ受け手段に装着
された複数の拡張メモリの運用順位を指定するセ
レクト信号を作成するセレクト信号作成手段と、
前記複数の拡張メモリの運用順位を外部から指定
するための運用順位指定手段と、該運転順位指定
手段出力と前記セレクト信号とを入力して前記運
用順位指定手段の指定に従う順位で前記セレクト
信号を前記拡張メモリ受け手段に付与する切換回
路手段と、を備えてなる信号処理装置。 a plurality of expansion memory receiving means for allowing attachment and detachment of a plurality of expansion memories; a selection signal generation means for generating a selection signal specifying the operational order of the plurality of expansion memories installed in the expansion memory reception means;
an operation order designation means for externally specifying the operation order of the plurality of expanded memories; and inputting the output of the operation order designation means and the selection signal, and outputting the selection signal in the order specified by the operation order designation means. A signal processing device comprising: switching circuit means provided to the extended memory receiving means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15200384U JPS6170242U (en) | 1984-10-08 | 1984-10-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15200384U JPS6170242U (en) | 1984-10-08 | 1984-10-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6170242U true JPS6170242U (en) | 1986-05-14 |
Family
ID=30710094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15200384U Pending JPS6170242U (en) | 1984-10-08 | 1984-10-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6170242U (en) |
-
1984
- 1984-10-08 JP JP15200384U patent/JPS6170242U/ja active Pending
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