JPS6178156A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce pattern dependence on the reading of a memory for forming a plurality of first aluminum reinforcing wires along the direction of a word line as the longitudinal direction of a memory cell plate. CONSTITUTION:A capacitance electrode 3 is shaped on the whole memory cell array on a field insulating film 18, and an aluminum reinforcing wire 5 is connected to the capacitance electrode 3 through contact holes formed at regular intervals at the end sections of a memory cell array. The reinforcing wire consists of the same aluminum layer as a word line WL, and extends in parallel with the word line WL. A reinforcing wire 6 is composed of the same aluminum layer as a data line DL, and extends in parallel with the data line DL. Since no memory cell is shaped and there is the field insulating film 18 in a region to which the reinforcing wire 6 is formed, a memory cell capable of connecting to the same data line is isolated at the center, and connected to different data lines 171, 172. A memory cell plate 10 is connected so that potential difference is minimized by the aluminum reinforcing wires, thus reducing a time constant to pattern dependence.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a technique effective for reducing the resistance of a memory cell plate of an open bit line type dynamic RAM.

[Background technology]

The oven bit line type (hereinafter referred to as the one-intersection method) and the folded line type (hereinafter referred to as the two-intersection method) are known mat arrangement methods for MOS dynamic RAM. Two bit lines, a pair of complementary bit lines, extend parallel to one side of the sense amplifier.One word line intersects these two bit lines, and a memory cell is located at the intersection. In addition, in the one-intersection method, two bit lines for one sense amplifier, that is, a pair of complementary bit lines, extend one on each side of the sense amplifier. On the other hand, one word line intersects, and a memory cell is formed at the intersection.

By the way, in the two-intersection method, polysilicon word lines are generally used. This word line is approximately 10Ω
The length of the memory cell array in the word line direction is limited, and is usually relatively short, 2 to 4M. Furthermore, since the two bit lines extend in the same direction with respect to the sense amplifier, there is relatively little capacitance imbalance.

Therefore, the dependence of capacitance unbalance on the pattern is also relatively good.

Also, in the one-cross point system, aluminum word lines are commonly used. This word line is 30-50m
Since it has a low resistance of Ω/gate, the length of the memory cell array in the word line direction can be relatively long.

However, according to the inventor's study, there are the following problems.

That is, since two bit lines are connected to the sense amplifier in both directions, information from different memory cell arrays is always input to the sense amplifier. However, since the potential of the capacitor electrode common to the memory cells of each memory cell array is likely to fluctuate due to noise or the like, an imbalance in capacitance occurs between the memory cell arrays. %, the degree of integration has increased, the number of memory cells has increased, and the area of the plate has become larger.

This becomes a big problem when the line width of the aluminum reinforcing wire for reducing the resistance of the memory cell plate becomes small. In other words, there is a problem in that the time constant required to reduce the changed potential of the capacitor electrode to a predetermined fixed potential becomes large.

That is, since the memory cell is formed of the first layer polysilicon, its resistance is large. For this reason, two aluminum reinforcing wires are formed parallel to each word iiK in the aluminum word line direction of the memory cell (memory cell length direction), and these aluminum reinforcing wires are connected to the pads 3. Even if such an aluminum reinforcing wire is formed, for example, if the length of the memory cell is 8 μm and the line width of the aluminum reinforcing wire is 8 μm, it will have a resistance of about 30 to 50 Ω. For this reason, in dynamic RAMs with more than IM bits, the time constant for pattern dependence becomes larger than several 1 on 8, which is a problem.

[Purpose of the invention]

An object of the present invention is to provide a technique for reducing pattern dependence during memory reading.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of WCL aluminum reinforcing lines are formed along the word line direction which is the longitudinal direction of the memory cell plate, and a plurality of WCL aluminum reinforcing lines are formed along the bit a direction of the memory cell with respect to the first aluminum reinforcing line. A second aluminum reinforcing wire is formed to interconnect the plurality of first aluminum reinforcing wires. Therefore, the resistance of the memory cell plate is reduced and the time constant for pattern dependent noise during memory read is reduced.

〔Example〕

FIG. 41 schematically shows a chip 1 of a one-intersection DRAM. In FIG. 1, 2 is a memory cell array, and 3 is a first polycrystalline silicon layer which is a capacitance electrode of a capacitor of a memory cell. Capacitor electrode 3 connects one memory cell array 2
This electrode is common to all memory cells in the memory cell array 2, and is provided in a shape substantially similar to that of the memory cell array 2.

A fixed potential 1, for example, a power supply potential VCC, is applied to the capacitor electrode 3. In order to eliminate the potential difference within the capacitor electrode 3, the first
And second aluminum reinforcements a5 and 6 are provided, and are connected to the capacitor electrodes at the X marks in the figure. The first aluminum reinforcing line 5 extends in the same direction as the word line WL and is made of the same first aluminum layer as the word iWL.

The second aluminum reinforcing line 6 extends in the same direction as the data line DL and is made of the same second aluminum layer as the data line DL.

4 is a peripheral circuit such as a sense amplifier and a decoder, and 7 is a bonding pad.

The relationship between the capacitor electrode 3 and the aluminum reinforcing wires 5 and 6 will be explained using FIGS. 2 to 5.

Cross-sections taken along lines R4-4 and 5-5 in FIG. 2 are shown in FIGS. 4 and 5, respectively. FIG. 3 is a diagram showing the shape of the special capacitor electrode 3. As shown in FIG. In FIG. 2, the upper layer wiring is partially removed.

In FIGS. 2 to 8gs, the capacitor of the memory cell is composed of a capacitive electrode 3 made of a first polycrystalline silicon layer, an insulating film 8, and a P-type semiconductor substrate l. The switching MO3FET of the memory cell consists of a gate electrode 11 made of a second polycrystalline silicon layer, a gate insulating film 10, an N-type semiconductor region 19, and a semiconductor substrate 1. Word line WL
consists of a first aluminum layer 18, which extends over the insulating film 14 and is connected to the gate electrode 11 through a contact hole. The data line DL mainly consists of the second layer aluminum layer 17, and extends perpendicularly to the word line WL on the insulating film 16, and passes through the contact hole to the first layer aluminum layer 15 provided only in the contact hole portion. It is connected to the third layer polycrystalline silicon layer 13 extending in the same shape below the line DL. 1st layer and 2nd layer, 2nd layer and 3rd layer
The polycrystalline silicon layers of the layers are insulated by insulating films 9 and 12, respectively.

A capacitor electrode 3 is provided on the field insulating film 18 over the entire memory cell array in the shape shown in FIG. At the end of the memory cell array, the capacitor electrode 3'VC and the first aluminum reinforcing wire 5 are connected through contact holes provided at regular intervals.

The first aluminum reinforcing line 5 is made of the same first aluminum layer as the word line WL. The first aluminum reinforcing line 5 extends parallel to the word line WL. Second aluminum reinforcement I! Reference numeral 6 is made of the same second aluminum layer as the data line DL. The second aluminum reinforcing line 6 extends parallel to the data line DL. No memory cells are formed in the area where the second aluminum reinforcement 1116 is provided;
A field insulating film 18 is present. For this reason, memory cells that can be connected to the same data line are separated at the center, and different data lines fi171, 172tcjl are connected.

The shape of the reinforcing wire for the capacitor electrode 3 is a ladder shape.
is taken. In this embodiment, five second aluminum reinforcing wires 40 are used, but the number can be increased or decreased as appropriate.

It can be seen that in the semiconductor device of the present invention described above, the memory cell plate 10 is connected by the first and second aluminum reinforcing wires 20 and 40 so that the internal potential difference is small. Therefore, compared to the resistance of about 30Ω of the conventional memory cell playback 10 using only the first aluminum reinforcing wire 2, the present invention can reduce the resistance by about 4Ω. Similarly, the time constant for pattern dependence can be reduced by about an order of magnitude. Therefore, it is possible to obtain a semiconductor device which has a small operation margin (but has a sufficient margin) with respect to pattern-dependent noise such as power supply voltage fluctuation access time and noise pressure, and has good testability.

Each of the first and second aluminum reinforcing wires 5.6,
By making the first layer and the second layer separately, the reinforcing wire of the above shape can be easily formed.

〔effect〕

As explained above, since aluminum reinforcing wires are formed in both the bit line direction and the word line direction with respect to the memory cell plate, the resistance of the memory cell plate, the resistance of the memory cell plates on both sides of the sense amplifier, and the resistance of the sense amplifier The resistance between the memory cell plates on either side can be reduced, reducing the time constant for pattern dependent noise in memory reads, which is determined by the total effective capacitance of the memory cell and the effective resistance of the memory cell plates.

Therefore, pattern dependence is reduced, and a product with a wide margin for each fence noise and good testability can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

Although the present invention is most effective when applied to a single-point memory cell type dynamic RAM, it is not limited thereto. Widely available.

[Brief explanation of drawings]

1 is a schematic diagram of the layout of a DRAM chip of the present invention; FIG. 2 is a partially enlarged view of the end of the memory cell array of the DRAM of FIG. 1; FIG. 3 is a diagram showing the shape of a capacitor electrode; 4 and 5 are cross-sectional views taken along section lines 4-4 and 5-5 in FIG. 2, respectively. 2... Memory mat, 3... Capacitor electrode, 5... First aluminum reinforcing wire, 6... Second aluminum reinforcing wire, 11... Gate electrode, 13... Third layer Polycrystalline silicon layer, 17...Data line, 18...Word line〇Figure 1 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A semiconductor device in which a reinforcing wire for reducing resistance is connected to a memory cell plate, the semiconductor device being electrically connected to the memory cell plate and extending along the word line direction of the memory cell. a plurality of first reinforcing wires formed on the plate; and a plurality of first reinforcing wires electrically connected to the first reinforcing wires and formed on the first aluminum reinforcing wires in the bit line direction. 1. A semiconductor memory device comprising: 2 reinforcing wires. 2. The semiconductor memory device according to claim 1, wherein the memory cell plate is made of polysilicon, and the first and second reinforcing lines are made of aluminum.