JPS6178352U - - Google Patents

Info

Publication number
JPS6178352U
JPS6178352U JP15983284U JP15983284U JPS6178352U JP S6178352 U JPS6178352 U JP S6178352U JP 15983284 U JP15983284 U JP 15983284U JP 15983284 U JP15983284 U JP 15983284U JP S6178352 U JPS6178352 U JP S6178352U
Authority
JP
Japan
Prior art keywords
memory access
direct memory
abnormal termination
circuit
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15983284U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15983284U priority Critical patent/JPS6178352U/ja
Publication of JPS6178352U publication Critical patent/JPS6178352U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電子線描画装置制御部と描画装置との
関係を示すブロツク図、第2図はDMA制御回路
のブロツク図、第3図は終了報告情報の例を示す
図である。 1…主記憶部、2…プロセツサ、3…システム
バス、4…DMA制御回路、5…CE、6…描画
装置。
FIG. 1 is a block diagram showing the relationship between the electron beam lithography apparatus control section and the lithography apparatus, FIG. 2 is a block diagram of the DMA control circuit, and FIG. 3 is a diagram showing an example of completion report information. DESCRIPTION OF SYMBOLS 1... Main memory part, 2... Processor, 3... System bus, 4... DMA control circuit, 5... CE, 6... Drawing device.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子線描画装置へのダイレクトメモリアクセス
データ転送において、正常終了か異常終了かを判
別する回路をもち、異常終了時のみ、異常終了詳
細情報を報告することを特徴とするダイレクトメ
モリアクセス制御回路。
A direct memory access control circuit comprising a circuit for determining whether the direct memory access data is terminated normally or abnormally in transferring data to an electron beam lithography apparatus, and reporting detailed information on the abnormal termination only in the case of abnormal termination.
JP15983284U 1984-10-24 1984-10-24 Pending JPS6178352U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15983284U JPS6178352U (en) 1984-10-24 1984-10-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15983284U JPS6178352U (en) 1984-10-24 1984-10-24

Publications (1)

Publication Number Publication Date
JPS6178352U true JPS6178352U (en) 1986-05-26

Family

ID=30717778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15983284U Pending JPS6178352U (en) 1984-10-24 1984-10-24

Country Status (1)

Country Link
JP (1) JPS6178352U (en)

Similar Documents

Publication Publication Date Title
JPS59192740U (en) computer equipment
JPS6178352U (en)
JPS5872050U (en) Receipt printing device
JPS60123051U (en) shared memory controller
JPS6030050U (en) Data memory access method
JPS61128739U (en)
JPS59125798U (en) Memory protection control device for data processing systems
JPS62162756U (en)
JPS5832543U (en) shared storage
JPS58147050U (en) information processing equipment
JPS58179836U (en) Field contact abnormality monitoring circuit
JPS5866446U (en) Abnormal convergence detection device
JPS61180337U (en)
JPS6020655U (en) Abnormality monitoring device for asynchronous bus-coupled computer system
JPS6127442U (en) Lock control device in plant equipment
JPS6095654U (en) data transfer control device
JPS61653U (en) DMA transfer circuit
JPS59118048U (en) Bidirectional direct memory access transfer circuit
JPS6065843U (en) Memory address expansion circuit
JPS63155548U (en)
JPS635542U (en)
JPS59100334U (en) computer system
JPS63179547U (en)
JPS5994393U (en) Image processing device
JPS6384650U (en)