JPS6180858A - Power mosfet - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] Related to the present invention & parasitic bipolar transistor prevention technology in a power MO8FET [Background Art] A power MOS l”ET has a horizontal offset gate structure and a vertical DSA (Diffusion 5el).
The latter has a structure in which a large number of cells are arranged at equal intervals vertically and horizontally to achieve high withstand voltage and large current, and is known to be used for high-voltage switching. It is being (Electronic Materials Published by Kogyo Kenkyukai, September 1981, P22-28) Each cell of this vertical DSA structure power MO3FET+7 consists of an n-type silicon substrate l having a K-rich Kn+ type layer 2 on the bottom as shown in Figure 3. As a drain, a p-type layer 3 and a source n+ type N6 are formed by 2JtK diffusion using a gate (poly-Si gate) 5 formed on a part of the surface of the drain via an insulating film 4 as a mask. The MO3FET operates so as to control the source-drain current passing through the p-type layer (channel portion) under the gate by applying a voltage.

This power MO8FET with vertical DSA structure has on-resistance R
0N is small, the ratio W/L of gate width W to gate length is large (obtained, the amplification factor gm can be large), the feedback capacitance Gr53 between the gate and drain is large, and the input capacitance ciss is large. It is suitable for power switching applications such as switching regulators and motor control.

The diode built into this power MO8FET (
p! Junction diode between u763 and n-type substrate 1)
DC using as flywheel diode FRD
/AC inverter bridge circuit (Fig. 5), paired MO8FETQ, ,Q, and Q3. Q3 and Q3 alternately switch, but in that case the following problem arises: Q, , Q- are on (Q2- Q
When Q, , Q are turned off from the state where s is off), the regenerative current IDR flows rapidly through the built-in diodes D2-D3,
When Q is turned on, it remains conductive while Q recovers. (See Figure 4) When this IDR flows into the parasitic bipolar transistor near the channel part, K.

(FIG. 3) turns on, and excessive current flows through the source n+ type region (1 cell), destroying the device.

[Invention Q] Purpose The present invention was made to overcome the above problems, and its purpose is to prevent current concentration due to the parasitic bipolar transistor in the Epower MO8FET and to increase the withstand voltage.

[Outline of the invention]

A brief overview of the typical inventions disclosed in this application is as follows. That is, in a power MO8FET, a parasitic bipolar transistor is eliminated by inserting a ballast resistor such as polysilicon into the north region. The object of the invention can be achieved by suppressing the operation and improving the withstand voltage.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which a vertical type D
It is a longitudinal cross-sectional view of one cell in the SA structure power MO3FET.

1 is the n-type silicon substrate that becomes the drain region and is the bottom? fii
&ICAa degree ° type layer 2'``'()''L/(7 electrode film'' 1 is provided, 3 is a p-type layer and a po IJ S is provided on its surface via an insulating film 4.
A gate 5 made of a material such as i is formed, and using this gate as a mask, an n-type diffusion layer 6 which becomes a source is formed on a part of the surface of the p-type layer 3. 7 is a ballast resistor connected to the source, made of poly-Si, for example, and K above the gate.
9 is a Sin film by CVD (vapor phase chemical deposition) method.
0 is a source electrode (wiring) made of Al (aluminum)
A part is connected to the p-type layer surface, and the other part is connected to the CVD-8
Q) Formed DSA woven power MO3FET connected to the ballast resistor 7 through the null-hole of the iO3 film 9.
1, and its AA' cross-sectional view corresponds to FIG.

In the figure, 3a is a contact hole through which the p-type layer 3 of the substrate is exposed, and 7a is a contact hole through which a ballast resistor 7 is exposed.6 The ballast resistor 7 is the same as the impurity-doped poly-Si that forms the gate IH electrode. things can be used.

This ballast resistance is determined by the doping amount of the JP impurity in the poly S1 planar shape (for example, the radial shape shown in FIG. 2), and its resistance value is, for example, 2O2 per cell.
The above shall apply.

〔effect〕

According to the present invention described in the embodiments above, the effects of the invention can be obtained for the following reasons.

FIG. 6 is an equivalent circuit diagram of the conventional power MO3FET shown in FIG. 3, which does not include a ballast resistor. In this case, the regenerative current I through the parasitic transistor (Kl, 2)
DR flows and current concentrates near the source. FIG. 8 is an overall plan view of a power MO8FET chip without a ballast resistor, in which many breakdowns (x marks) due to current concentration are seen near the source/ponding pad S.

FIG. 7 is an equivalent circuit diagram of a power MO8FET according to the present invention including a ballast resistor R8. In this case, by inserting Rs, a regenerative current I to a parasitic bipolar transistor is generated. R can be dispersed and concentration can be avoided. Figure 9 is an overall plan view of a power MO8FET chip including a ballast resistor, and no damage was observed near the source/ponding pad S.

As described above, according to the present invention, the parasitic bipolar transistor operation of the cells around the source/ponding pad S is suppressed due to the ballast effect, and the breakdown resistance is improved by 10 to 20 times. That is, in contrast to the conventional example that does not include the ballast resistor R8, the breakdown resistance is 01 to 0.2 A.
In the example of the present invention including a ballast resistor R8, the withstand capacity is 1.5
[Field of Application] The present invention is particularly effective when applied to power MOS FETs used in DC/AC inverter bridge circuit diagrams for motor control and the like.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of one cell portion of a power MO3FET having a vertical DNA structure, showing an embodiment of the present invention. Figure 2 is a plan view of the power MO8FET shown in Figure 1. Figure 3 is the conventional vertical DNA structure power MO3FE.
It is a longitudinal cross-sectional view of T. FIG. 4 is a curve diagram showing the form of the regenerative current IDH after the forward current IF of the power MO8FET is cut off. FIG. 5 is a circuit diagram showing an example of a DC/AC inverter tab 979 circuit. The sixth factor, FIG. 7, is an equivalent circuit diagram of the power MO3FET. FIGS. 8 and 9 are overall plan views of the power MO3FET chip, showing the state of current concentration. DESCRIPTION OF SYMBOLS 1...n-type Si base (drain), 2...n+ type layer, 3...p-type layer, 4...insulating film, 5...gate (poly-Si), 6... n+ type scattered layer source), 7.
...Ballast resistance (Po IJ S i ), 8.9...
Insulating film, 10...aluminum electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. A power MOS characterized in that a ballast resistor is inserted in the source region so as to suppress the operation of a parasitic bipolar transistor in the power MOSFET.
FET. 2. The power MOSFET according to claim 1, wherein the ballast resistor is made of polysilicon, which is a gate electrode forming material. 3. The above power MOSFET is a vertical DSA structure MOSF
The power MOSFET according to claim 1 or 2, which is an ET.