JPS6181230U - - Google Patents
Info
- Publication number
- JPS6181230U JPS6181230U JP16569884U JP16569884U JPS6181230U JP S6181230 U JPS6181230 U JP S6181230U JP 16569884 U JP16569884 U JP 16569884U JP 16569884 U JP16569884 U JP 16569884U JP S6181230 U JPS6181230 U JP S6181230U
- Authority
- JP
- Japan
- Prior art keywords
- stage
- counter
- counting
- clock signal
- nth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Description
第１図はこの考案の一実施例を示す回路図、第
２図は第１図の動作を示すタイムチヤート、第３
図は従来装置の回路図である。
１ａ〜１ｈ…フリツプフロツプ、２ａ〜２ｕ…
ゲート回路。
Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a time chart showing the operation of Fig. 1, and Fig. 3 is a circuit diagram showing an embodiment of this invention.
The figure is a circuit diagram of a conventional device. 1a-1h...Flip-flop, 2a-2u...
gate circuit.
Claims (1)
ーブ接続したカウンタをｎ段（ｎは正の自然数）
縦続接続して最下位段を第１段目として最上位段
を第ｎ段目として構成したカウンタ回路において
、０から８までのカウントは２進カウンタ動作を
行なわせ、９をカウントする時は第２段目のカウ
ンタにクロツク信号を与えず、１０をカウントす
る時は第１段目と第ｎ段目のカウンタにクロツク
信号を供給する切換回路を備え、クロツク信号は
最大２段のゲート回路によつて構成されることを
特徴とするカウンタ回路。 N-stage counter with D-type flip-flops connected as master and slave (n is a positive natural number)
In a counter circuit configured in cascade, with the lowest stage as the first stage and the highest stage as the nth stage, counting from 0 to 8 is performed by a binary counter operation, and when counting 9, the counter circuit is configured as the first stage and the highest stage is the nth stage. When counting 10 without giving a clock signal to the second stage counter, a switching circuit is provided to supply a clock signal to the first and nth stage counters, and the clock signal can be sent to a maximum of two stage gate circuits. A counter circuit characterized in that it is configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16569884U JPS6181230U (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16569884U JPS6181230U (en) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181230U true JPS6181230U (en) | 1986-05-29 |
Family
ID=30723538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16569884U Pending JPS6181230U (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181230U (en) |
-
1984
- 1984-11-02 JP JP16569884U patent/JPS6181230U/ja active Pending
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