JPS6181329U - - Google Patents
Info
- Publication number
- JPS6181329U JPS6181329U JP16662884U JP16662884U JPS6181329U JP S6181329 U JPS6181329 U JP S6181329U JP 16662884 U JP16662884 U JP 16662884U JP 16662884 U JP16662884 U JP 16662884U JP S6181329 U JPS6181329 U JP S6181329U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- capacitor
- integrating circuit
- differentiating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第1図は本考案の実施例を示す回路図、第2図
は各部の波形を示す波形図、第3図は従来例を示
す回路図である。
主な図番の説明、7…微分回路、10…積分回
路、12…コンデンサ、14,17…スイツチン
グトランジスタ、15…ダイオード、16…レベ
ル保持用コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms at various parts, and FIG. 3 is a circuit diagram showing a conventional example. Explanation of main figure numbers, 7...Differential circuit, 10...Integrator circuit, 12...Capacitor, 14, 17...Switching transistor, 15...Diode, 16...Level holding capacitor.
Claims (1)
ラインに接続されコンデンサを含んで構成される
積分回路と、該積分回路の出力端と前記微分回路
の出力端にコレクタエミツタ路が接続された第1
スイツチングトランジスタと、前記微分回路の出
力を整流する整流回路と、該整流回路に接続され
たレベル保持用コンデンサと、該レベル保持用コ
ンデンサの出力が抵抗を介してベースに入力され
前記積分回路のコンデンサに並列にコレクタエミ
ツタ路が接続された第2スイツチングトランジス
タとを有し、前記積分回路の出力をリセツト信号
としたことを特徴とするリセツト回路。 a differentiating circuit connected to a power supply line, an integrating circuit connected to the power supply line and including a capacitor, and a collector-emitter path connected to an output terminal of the integrating circuit and an output terminal of the differentiating circuit. 1
A switching transistor, a rectifier circuit that rectifies the output of the differentiating circuit, a level holding capacitor connected to the rectifying circuit, and an output of the level holding capacitor that is input to the base of the integrating circuit through a resistor. 1. A reset circuit comprising: a second switching transistor having a collector-emitter path connected in parallel to a capacitor; and an output of the integrating circuit is used as a reset signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16662884U JPS6181329U (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16662884U JPS6181329U (en) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181329U true JPS6181329U (en) | 1986-05-30 |
Family
ID=30724436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16662884U Pending JPS6181329U (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181329U (en) |
-
1984
- 1984-11-02 JP JP16662884U patent/JPS6181329U/ja active Pending
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