JPS6181344U - - Google Patents
Info
- Publication number
- JPS6181344U JPS6181344U JP16665684U JP16665684U JPS6181344U JP S6181344 U JPS6181344 U JP S6181344U JP 16665684 U JP16665684 U JP 16665684U JP 16665684 U JP16665684 U JP 16665684U JP S6181344 U JPS6181344 U JP S6181344U
- Authority
- JP
- Japan
- Prior art keywords
- data
- read
- circuit
- reading
- pulse train
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
図はすべて本考案の実施例を示し、第１図は本
考案による媒体記録データの読込回路の構成を読
取装置およびデータ処理回路とともに示すブロツ
ク回路図、第２図は本考案回路中の読取開始検出
回路の具体構成例を示す回路図、第３図は本考案
回路が読取装置から受ける読取パルスおよび信号
の波形を示す波形図である。図において、
１０：読取装置としてのカードリーダ、１２：
データの記録媒体としてのカード、２０：読込回
路、２１：データ変換回路、２２：読取開始検出
回路、２３：読込指令回路、２４：一時記憶回路
、３０：データ処理回路、３１：ＣＰＵ、３２：
ＲＡＭ、ＣＳ：カード検出信号、ＲＣＰ：読取ク
ロツクパルスないし読取クロツクパルス列、ＲＤ
Ｐ：読取データパルスないしは読取データパルス
列、ＲＳ：読込指令、Ｔ１：読取データパルス列
中のデータ開始信号部、Ｔ２，Ｔ３：読取データ
パルス列中の実データ部、である。
The figures all show embodiments of the present invention. Figure 1 is a block circuit diagram showing the configuration of a reading circuit for medium recorded data according to the present invention together with a reading device and a data processing circuit, and Figure 2 is a block circuit diagram showing the start of reading in the circuit of the present invention. FIG. 3 is a circuit diagram showing a specific example of the configuration of the detection circuit. FIG. 3 is a waveform diagram showing the waveforms of reading pulses and signals that the circuit of the present invention receives from the reading device. In the figure, 10: card reader as a reading device, 12:
Card as a data recording medium, 20: reading circuit, 21: data conversion circuit, 22: reading start detection circuit, 23: reading command circuit, 24: temporary storage circuit, 30: data processing circuit, 31: CPU, 32:
RAM, CS: Card detection signal, RCP: Read clock pulse or read clock pulse train, RD
P: read data pulse or read data pulse train; RS: read command; T1: data start signal part in the read data pulse train; T2, T3: actual data part in the read data pulse train.
Claims (1)
取りに当つて読取クロツクパルス列とデータ開始
信号部を含む読取データパルス列とを発する読取
装置からの読み取りデータをデータ処理回路に読
み込むための回路であつて、読取装置からの読取
データパルス列をシリアルに受けこれを所定ビツ
ト長のパラレルデータに変換するデータ変換回路
と、該データ変換回路の出力を受け読取データパ
ルス列中のデータ開始信号部を検出する読取開始
検出回路と、該読取開始検出回路からの検出信号
により始動し読取クロツクパルス列からデータの
データ処理回路への読取周期を決定して読込指令
を発する読込指令回路と、該読込指令を受けてデ
ータ変換回路からパラレルデータを読み込んで一
時的に保持する一時記憶回路とを備え、データ処
理回路に前記読込指令を割込指令として与えて前
記一時記憶回路に保持されているパラレルデータ
をデータ処理回路に並列的に読み込むようにした
ことを特徴とする媒体記録データの読込回路。 A circuit for reading read data from a reading device that emits a read clock pulse train and a read data pulse train including a data start signal part into a data processing circuit when reading data stored in a recording medium such as a card. , a data conversion circuit that serially receives a read data pulse train from a reading device and converts it into parallel data of a predetermined bit length; and a read start circuit that receives the output of the data conversion circuit and detects a data start signal part in the read data pulse train. a detection circuit, a read command circuit that is started by a detection signal from the read start detection circuit, determines the read cycle of data to the data processing circuit from the read clock pulse train, and issues a read command; and a temporary storage circuit that reads parallel data from the conversion circuit and temporarily holds it, and provides the read command to the data processing circuit as an interrupt command to transfer the parallel data held in the temporary storage circuit to the data processing circuit. A reading circuit for reading data recorded on a medium, characterized in that data is read in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16665684U JPS6181344U (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16665684U JPS6181344U (en) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181344U true JPS6181344U (en) | 1986-05-30 |
Family
ID=30724466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16665684U Pending JPS6181344U (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181344U (en) |
-
1984
- 1984-11-02 JP JP16665684U patent/JPS6181344U/ja active Pending
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