JPS6183390U - - Google Patents
Info
- Publication number
- JPS6183390U JPS6183390U JP16890584U JP16890584U JPS6183390U JP S6183390 U JPS6183390 U JP S6183390U JP 16890584 U JP16890584 U JP 16890584U JP 16890584 U JP16890584 U JP 16890584U JP S6183390 U JPS6183390 U JP S6183390U
- Authority
- JP
- Japan
- Prior art keywords
- reference signal
- modulated wave
- phase modulated
- circuit
- demodulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の一実施例を示す図である。第
２図はＰＳＫ復調器の動作を示す波形図である。
第３図乃至第６図は従来例に関し、第３図は電子
スチルカメラの記録信号を示す図、第４図は電子
スチルカメラの概略ブロツク図、第５図はＰＳＫ
復調器の回路ブロツク図、第６図はＰＳＫ信号の
変調を説明するための図である。
ｇ，ｇ′……ＰＳＫ信号（位相変調波信号）、
ｈ……基準信号、ｉ……復調データ、Ｎ，Ｐ……
ラツチパルス、１６……ＰＳＫ復調器（位相変調
波復調器）、３０……復調回路、４０……基準信
号作成回路、６０……ホールド回路。
FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a waveform diagram showing the operation of the PSK demodulator.
3 to 6 relate to conventional examples, FIG. 3 is a diagram showing recording signals of an electronic still camera, FIG. 4 is a schematic block diagram of an electronic still camera, and FIG. 5 is a PSK system.
FIG. 6, a circuit block diagram of the demodulator, is a diagram for explaining the modulation of the PSK signal. g, g'...PSK signal (phase modulated wave signal),
h...Reference signal, i...Demodulated data, N, P...
Latch pulse, 16...PSK demodulator (phase modulated wave demodulator), 30... demodulation circuit, 40... reference signal generation circuit, 60... hold circuit.
Claims (1)
を出力する復調回路と、前記位相変調波信号を同
期入力とすると共に前記復調データを位相制御入
力とし前記基準信号を作成する基準信号作成回路
とを、備える位相変調波復調器に於いて、 前記復調回路の後段に配されてデータ切り換え
点直後のラツチパルスによつて、復調出力をラツ
チして前記復調データを導出するホールド回路を
、備えることを特徴とする位相変調波復調器。[Claims for Utility Model Registration] A demodulation circuit that inputs a phase modulated wave signal and a reference signal and outputs demodulated data; A phase modulated wave demodulator is provided with a reference signal generating circuit to generate a reference signal, and the demodulated output is latched by a latch pulse immediately after the data switching point, which is arranged after the demodulating circuit and derives the demodulated data. A phase modulated wave demodulator comprising a hold circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16890584U JPH0411425Y2 (en) | 1984-11-07 | 1984-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16890584U JPH0411425Y2 (en) | 1984-11-07 | 1984-11-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6183390U true JPS6183390U (en) | 1986-06-02 |
| JPH0411425Y2 JPH0411425Y2 (en) | 1992-03-23 |
Family
ID=30726665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16890584U Expired JPH0411425Y2 (en) | 1984-11-07 | 1984-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0411425Y2 (en) |
-
1984
- 1984-11-07 JP JP16890584U patent/JPH0411425Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0411425Y2 (en) | 1992-03-23 |
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