JPS618400U - Status judgment circuit - Google Patents
Status judgment circuitInfo
- Publication number
- JPS618400U JPS618400U JP8939784U JP8939784U JPS618400U JP S618400 U JPS618400 U JP S618400U JP 8939784 U JP8939784 U JP 8939784U JP 8939784 U JP8939784 U JP 8939784U JP S618400 U JPS618400 U JP S618400U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- output
- abnormal
- normal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
Claims (3)
異常パルスの一方を選択する第１の選択手段と、該選択
手段により選択された正常パルス又は異常パルスを予め
定めた分周比で分周する分周手段と、二つの入カパルス
の各個数のいずれが予め定めた計数値に達するかを示す
計数結果に従って異常状態出力と正常状態出力を出す計
数手段とく該計数手段が前記異常状態出力を− 出した
ときにセットされて異常状態を示す異常出力を出し該正
常状態出力を出したときにリセットされて正常状態を示
す正常出力を出すフリツプ・フロツプと、該正常出力に
より前記選択手段に前記異常パルスを選択させ該異常出
力により前記選択手段に前記正常パルスを選択させる制
御手段手段と、該正常出力が出力されているときには前
記分周手段の出力パルスと前記異常ノシレスとを前記計
数手段に計数させかつ前記異常出力が出力されていると
きには前記分周手段の出力パルスと前記正常パルスとを
前記計数手段に計数させる第２の選択手段とを備え、前
記フリップ・フロツプからの異常出力と正常出′力とを
判定結果としてとり出子ように構成されたステイタス判
定回路。(1) A first selection means for selecting either a normal pulse or an abnormal pulse corresponding to each binary status, and dividing the normal pulse or the abnormal pulse selected by the selection means at a predetermined frequency division ratio. a frequency dividing means, and a counting means for outputting an abnormal state output and a normal state output according to a counting result indicating which of the two input pulses reaches a predetermined count value. a flip-flop which is set to output an abnormal output indicative of an abnormal condition when the output is output, and is reset to output a normal output indicating the normal condition when the output of the normal condition is output; control means means for selecting a pulse and causing the selection means to select the normal pulse according to the abnormal output; and when the normal output is output, the output pulse of the frequency dividing means and the abnormal pulse are counted by the counting means. and a second selection means for causing the counting means to count the output pulses of the frequency dividing means and the normal pulses when the abnormal output is being output, A status determination circuit configured to extract power as a determination result.
ルスを前記分周手段により分周した異常分周パルスをア
ップ人カパルスとしかつ前記正常パルス又は該正常パル
スを前記分周手段により分周した正常パルスをダウン入
力とし前記予め定めた計数値に相当するスケールを有す
るアップダウンカウンタと、該アップダウンカウンタの
出力が前記予め定めた計数値に達したときに前記フリツ
プ●フロツプにセット入力を出す第１−のデイテクタと
、該アンプダウンカウンタの出力が前記予め定めた計数
値に達しないときに前記フロツプ・フリップにリセット
入力を出す第２のデイテクタとを備えた実用新案登録請
求の範囲第１項に記載のステイタス判定回路。(2) The counting means uses the abnormal pulse or the abnormal frequency-divided pulse obtained by dividing the abnormal pulse by the frequency dividing means as an up-scale pulse, and divides the normal pulse or the normal pulse by the frequency dividing means. an up-down counter with a scale corresponding to the predetermined count value, with the normal pulse input as a down input, and a set input to the flip-flop when the output of the up-down counter reaches the predetermined count value. and a second detector that outputs a reset input to the flip-flop when the output of the amplifier down counter does not reach the predetermined count value. The status determination circuit according to item 1.
スを前記分周手段により分周した異常分周パルスを計数
して第１の所定の計数値に達したときに前記フリツプ●
フロツブにセット入力を印加する第１のカウンタと、前
記正常パルス又は該正常パルスを前記分周手段により分
周した正常分周パルスを計数して第２の所定の計数値に
達したときに前記フリツプ●フロツプにリセット入力を
印加する第２のカウンタと、前記セット入力又は前記リ
セット入力が発生したときに前記第１のカウンタと前記
第２のカウンタとをリセットするリセット手段とを備え
た実用新案登録請求の範囲第１項に記栽のステイタス判
定回路。(3) When the counting means counts the abnormal pulse or the abnormal frequency-divided pulse obtained by dividing the abnormal pulse by the frequency dividing means and reaches a first predetermined count value, the flip
a first counter that applies a set input to a float; and a second counter that counts the normal pulse or a normal frequency-divided pulse obtained by dividing the normal pulse by the frequency dividing means, and when a second predetermined count value is reached. A utility model comprising a second counter that applies a reset input to the flip-flop, and reset means that resets the first counter and the second counter when the set input or the reset input occurs. Claim 1: A circuit for determining the status of cultivation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8939784U JPS618400U (en) | 1984-06-18 | 1984-06-18 | Status judgment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8939784U JPS618400U (en) | 1984-06-18 | 1984-06-18 | Status judgment circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS618400U true JPS618400U (en) | 1986-01-18 |
| JPH049676Y2 JPH049676Y2 (en) | 1992-03-10 |
Family
ID=30643435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8939784U Granted JPS618400U (en) | 1984-06-18 | 1984-06-18 | Status judgment circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS618400U (en) |
-
1984
- 1984-06-18 JP JP8939784U patent/JPS618400U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH049676Y2 (en) | 1992-03-10 |
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