JPS6187428A - PPL locking method - Google Patents

Abstract

PURPOSE:To lock a PLL as long as an input signal is within the lock range even if it is at the outside of the acquisition range by generating a signal changing gradually after application of power, and controlling the time constant of a VCO to make the VCO oscillate in a sweep mode. CONSTITUTION:A power supply section 11 in a toner density controller of a copying machine generates a bipolar voltage on the basis of an earth potential from a power input and applies it to an oscillator 12. The oscillator 12 is oscillated in a frequency in response to the toner density and applies the result to a PLL14 provided to an FM demodulator 13 via a capacitor C4. A current of resistors R9, R10 is changed gradually after the application of power by a time constant control circuit comprising resistors R17, R19, a C10 and a transistor TR4 in the demodulator 13 to apply sweep oscillation to the self-running frequency of the VCO in the PLL14 so as to lock the PLL14 to an output frequency of the oscillator 12. The output of the demodulator 13 is swung from a +Vcc to a -Vcc on the basis of OV by an integration device 16 through a buffer 15 and the R9 is adjusted so as to attain the output voltage of the PLL14 to 'O' V.

Description

[Detailed Description of the Invention] The present invention is based on PLL (Phase tacked loop).
The present invention relates to a locking method for reliably locking p) to an input signal within a lock range.

The PLL has a capture range centered around the free-running frequency of the voltage controlled oscillator (hereinafter referred to as vCO), which transitions from the non-lock state fm to the lock state if the frequency of the input signal is within this range, and A lock range is defined within which the locked state can be maintained when locked to a specific number. Commercially available PLL ICs have a capture range of about ±10% of the free-running frequency of the vCO, and a lock range of about several tens of percent of the free-running frequency of the vCO, although there are differences depending on how they are used. Therefore, there was a drawback that the PLL could not lock onto an input signal whose frequency fluctuation range was outside the capture range, and the PLL could not function.

The present invention solves the above-mentioned drawbacks, and even if the frequency fluctuation range of the input signal is outside the capture range, the PLL can be locked to the input signal as long as it is within the lock range.
The purpose is to provide a locking method for L.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example in which the present invention is implemented in a toner density controller of a copying machine. 6. A power supply section 11 is a circuit that generates positive and negative power supplies (+Vcc', -Vcc) from one power supply input, and includes a resistor R1. , R2, an operational amplifier ul, transistors TR1, , TR2, and positive and negative power supplies determined by the voltage division ratio of resistors RL and R2 with the ground potential as a reference. 6V
The oscillator 12 is a transistor TR.
3. Coil, capacitors C2, C3, resistors R3 to R6
This is a Colpitts-type oscillator that oscillates at a frequency determined by the capacitors C2 and C3 and the coil. The coil is installed in the developer flow path of the imager in a copying machine, and the inductance of the coil L changes depending on the mixing ratio of the imager, which is a mixture of iron powder and toner, that is, the toner concentration, and the oscillator 12 is activated. The toner oscillates at a frequency corresponding to 211 degrees. The FM demodulator 13 is a PLL IC (NE565^
, manufactured by Signetics) 14, and the output of the oscillator 12 is connected to the PL via a coupling capacitor C4.
It is input to L14. In this demodulator 13, resistors R7 and R8 constitute an input bias circuit of the PLL 14, and diodes DI and D2 constitute an amplitude limiter and function to protect the input circuit.

Resistor R9, RIO and capacitor C5 are l'LL 14
This element determines the free-running frequency of the VCO in the VCO, and by varying the free-running frequency of the VCO by varying the resistor R9, the output level of the FM demodulator 13 can be changed and the toner density can be adjusted. Buffer 15 after the FM demodulator 13. As is clear from the integrator 16, the output of the final stage swings from the +Vcc side to the -Vcc side with Ov as the reference, so when the toner concentration is a predetermined value, the output of the PLL 14, that is, the voltage between its 6th and 7th terminals. Resistor R9 is adjusted so that OV becomes OV. Capacitor C6゜C7 is PL
It constitutes a low-pass filter for the feedback loop of L14 and is for stabilizing the control loop. The buffer 15 includes an operational amplifier u2, a capacitor C8, and resistors Rts to R14, and buffers the output of the PLL 14 to prevent overload. The integrator 16 consists of an operational amplifier u3°, a capacitor C9, resistors R15 and R16, and a buffer 15.
Level detection is performed by integrating the output of Ov as a reference.
Level detection by the integrator 16 was performed by PLL 1.
This is because the output of No. 4 includes ripples, and because the output includes ripples due to poor circulation of the developer, and to avoid output caused by ripples with high frequencies. Although the part where toner is replenished into the developer of the developing device is not shown here, when the output of the integrator 16 is at a low level, the bottle containing the replenishing toner is rotated, and the dense toner is poured into the developing tank. It is structured to guide you.

PLL (NE565A) 14 in adjusting resistor R9
According to the characteristics, when the oscillation frequency fr of the oscillator 12 and the free-running frequency fo of the vCO are matched at a predetermined toner concentration, the voltage between the terminals 6 and 7 of the PLL 14 is not necessarily Ov, and the maximum voltage is 200 m from the catalog value. Since there is an offset of V, it is necessary to adjust the free running frequency fO by changing the resistor R9 to cancel this maximum of 200 mV. The amount of adjustment is determined by the sensitivity of FM demodulation, and under the worst conditions, 20
%, it is necessary to shift the free-running frequency fO. However, in this PLL 14, the capture range is approximately ±10
%, the lock range is about 60%, so if the free-running frequency fO is shifted by 20%, the oscillation frequency fr will deviate from the capture range by adjusting the free-running frequency fo, so conventionally, when the power is turned on, the PLL 14 was not locked to the output signal of the oscillator 12, and a situation occurred where the toner concentration controller could not function. In this embodiment, a time constant circuit control circuit consisting of resistors RL7 to R19, a capacitor 10, and a transistor TR4 is provided.
By gradually changing the RIO current after the power is turned on, the rise of the voltage applied to the free-running frequency determining element R9 of vCO and RIO is made into an exponential function, and the charging current to the capacitor C5 decreases in the middle of the rise. VC
Sweep oscillation of the free running frequency fo of O to generate PLL 14
is made to reliably lock to the output signal of the oscillator 12. Fo in FIG. 3 shows this state in terms of the exchange of the terminal voltage of capacitor C5. f in Figure 3
r is the output waveform of the oscillator 12, and since a predetermined voltage is applied to the oscillator 12 when the power is turned on, the oscillator 12 oscillates at a constant frequency fr from the beginning. FIG. 2 shows the relationship between fr and fO with frequency as the horizontal axis. As mentioned above, fo may become higher than fr and exceed the capture range. Even in this case, if you sweep fo as shown in Figure 3, fo will gradually move from a low frequency to a high frequency and pass each other with fr, or fr will enter the cab or charge range and PLL 14 will lock. become a state. Since the PLL 14 operates in the lock range shown by the dashed line in FIG. 2 when it is in the lock state, reliable operation is possible even with large fluctuations in fr caused by ripples in the flow of toner.

After the power is turned on, the current of the light emitting diode LED gradually increases, and the phototransistor PT receives the light.
R controls the currents of resistors R9 and RIO to sweep fo from a low value to a high value. In addition, in the above embodiment, as shown in FIG. 4, the resistor R17 and the capacitor CI
A resistor R is connected in parallel with the phototransistor PTR, with the
If 20 is connected, fo can be swept from a high value to a low value. Such a sweep is f for fr
Used when o is shifted to the lower side. Resistance R
20 is a resistor for determining fo when the phototransistor PTR is cut off. Capacitor C5 can also be similarly controlled to sweep fo. As mentioned above, the NE565 manufactured by Signetics is used as a PLL.
Although an example using PLL has been described, the present invention is applicable to PLL in general. This is especially necessary when used in motor speed control devices, toner density controllers for copying machines, etc., where the input frequency shift band is wide, and the PLL can perform reliable control. If the power supplies for the oscillator 12 (or signal receiver) and the PLL 14 are different, the fO of the PLL may be swept when the power supply that rises slowly rises.

As described above, according to the PLL locking method according to the present invention, the CO of the PLL is caused to sweep oscillate by controlling the time constant circuit after power is turned on, so even if the frequency fluctuation of the PLL input signal is outside the capture range, If it is within the lock range, the PLL can be put into a locked state, and the PLL can be used even when the input frequency fluctuations are wide.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a toner density controller to which the present invention is applied, FIGS. 2 and 3 are diagrams for explaining the present invention, and FIG. 4 is a circuit diagram for explaining the present invention in detail. It is a diagram. 11...Power supply unit, 13...FM demodulator, 14...
...PLL, R9, RIO...Resistance, C5...
・Capacitor, R17-R20...Resistance, C10...
...Capacitor, TR4...Transistor, LE
D...Light emitting diode, PTR...Phototransistor.

Claims (1)

[Claims] In a PPL having a voltage controlled oscillator, a signal that gradually changes after the power is turned on is generated, and this signal controls the time constant circuit of the voltage controlled oscillator to cause the voltage controlled oscillator to sweep oscillate, thereby keeping the PPL within the lock range. A PLL locking method that includes a time constant circuit control circuit that locks to the input signal.