JPS6187433A - FM tuner image trap circuit - Google Patents
FM tuner image trap circuitInfo
- Publication number
- JPS6187433A JPS6187433A JP59208487A JP20848784A JPS6187433A JP S6187433 A JPS6187433 A JP S6187433A JP 59208487 A JP59208487 A JP 59208487A JP 20848784 A JP20848784 A JP 20848784A JP S6187433 A JPS6187433 A JP S6187433A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- image
- antenna
- capacitor
- trap circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Filters And Equalizers (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＦＭチューナのイメージトラップ回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image trap circuit for an FM tuner.
従来例の構成とその問題点
従来例の構成を第４図に示す。 バリキャップ（ＶＣ，
）の容量に比べて、バイパスコンデンサ（Ｃ１）の容量
は充分大きい・ので、バリキャップ（ＶＣｔ）の容量と
同調用コンデンサ（Ｃ２）の容量との並列容量とコイル
（Ｌｌ）との直列共振回路が、アンテナ端に挿入されて
いることになる。コイル（Ｌ工）のインダクタンスと同
調用コンデンサ（Ｃ２）との容量とを適当に選ぶことに
より、この直列共振回路の共振周波数を、受信周波数の
イメージ周波数に設定している。イメージ周波数でイン
ピーダンスが低くなる為、アンテナから入ってきたイメ
ージ信号は、低インピーダンスでアースにシャントされ
る。なお第４図において、（Ｒ１）はバリキャップ電圧
印加用抵抗、（１）はアンテナ同調回路、（２）は高周
波増幅段、（３）はイメージトラップ回路である。Configuration of the conventional example and its problems The configuration of the conventional example is shown in FIG. Varicap (VC,
) Since the capacitance of the bypass capacitor (C1) is sufficiently large compared to the capacitance of is inserted at the end of the antenna. By appropriately selecting the inductance of the coil (L) and the capacitance of the tuning capacitor (C2), the resonant frequency of this series resonant circuit is set to the image frequency of the receiving frequency. Since the impedance is low at the image frequency, the image signal coming in from the antenna is shunted to ground with low impedance. In FIG. 4, (R1) is a resistor for applying a varicap voltage, (1) is an antenna tuning circuit, (2) is a high frequency amplification stage, and (3) is an image trap circuit.
しかしながら、直列共振回路では、共振回路のＱを高く
とるのがむずかしく、かつ、アンテナを接続した時、共
振回路のＱがダンプされて負荷Ｑが低くなるので、急峻
な減衰特性が得られない。However, in a series resonant circuit, it is difficult to make the Q of the resonant circuit high, and when an antenna is connected, the Q of the resonant circuit is dumped and the load Q becomes low, so a steep attenuation characteristic cannot be obtained.
第５図に従来のイメージトラップ回路によるアンテナ端
子での減衰特性を示す。この様に、従来回路では、イメ
ージ周波数での減衰量が充分得られないのみならず、受
信帯域内においても、多少減衰し、その結果、帯域内で
の感度が悪化するという問題があった。FIG. 5 shows the attenuation characteristics at the antenna terminal of a conventional image trap circuit. As described above, the conventional circuit not only cannot obtain a sufficient amount of attenuation at the image frequency, but also has some attenuation within the reception band, resulting in a problem in that the sensitivity within the band deteriorates.
発明の目的
本発明は」二記従来の欠点を解消するもので、受信帯域
内での感度を悪化させずに、イメージ周波数を減衰させ
ることのできるＦＭチューナのイメージトラップ回路を
提供することを目的とする。OBJECTS OF THE INVENTION The present invention solves the above-mentioned drawbacks of the conventional art, and an object of the present invention is to provide an image trap circuit for an FM tuner that can attenuate image frequencies without deteriorating sensitivity within the receiving band. shall be.
発明の構成
」二記目的を達成するため、本発明のＦＭチューナのイ
メージトラップ回路は、可変同調素子としてのバリキャ
ップとコイルと第１のコンデンサとを並列接岐した並列
共振回路と、この並列共振回路とアンテナ入力端との間
に接続された第２のコンデンサとを備えた構成としたも
のである。In order to achieve the second object of "Structure of the Invention", the image trap circuit of the FM tuner of the present invention includes a parallel resonant circuit in which a varicap as a variable tuning element, a coil, and a first capacitor are connected in parallel; This configuration includes a second capacitor connected between the resonant circuit and the antenna input end.
かかる構成によれば、コイルのインダクタンスと第１の
コンデンサの容量とを適当に選んで、並列共振回路の同
調点を、受信周波数のイメージ周波数に設定することに
より、ＦＭチューナが希望信号を受（ａ している時、
並列共振回路はイメージ周波数に同調し、かつ共振回路
のＱも高くとれる為、イメージ周波数において、共振回
路のインピーダンスは充分低い、純抵抗分になる。さら
に第２のコンデンサも、イメージ周波数においては充分
低いインピーダンスになる為、イメージ周波数のみが、
低インピーダンスでアースにおとされ、受信帯域内の周
波数においては、共振回路のＱが充分高い為高インピー
ダンスになり、減衰することがなく、感度低下もおこら
ない。According to this configuration, the FM tuner receives the desired signal by appropriately selecting the inductance of the coil and the capacitance of the first capacitor and setting the tuning point of the parallel resonant circuit to the image frequency of the reception frequency. a When you are doing
Since the parallel resonant circuit is tuned to the image frequency and the Q of the resonant circuit can be set high, the impedance of the resonant circuit at the image frequency becomes a sufficiently low pure resistance component. Furthermore, since the second capacitor also has a sufficiently low impedance at the image frequency, only the image frequency
It is grounded with low impedance, and at frequencies within the reception band, the Q of the resonant circuit is sufficiently high, so it becomes high impedance, and there is no attenuation and no decrease in sensitivity.
実施例の説明
以下、本発明の一実施例について、図面に基づいて説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例におけるＦＭチューナのイメ
ージトラップ回路を含むアンテナ回路の回路図で、（Ｃ
３）はコンデンサ、（Ｌ２）はコイル、（ＶＣ，）はべ
りキャップ、（Ｃ４）は同調用コンデンサ、（Ｃ９）は
バイパスコンデンサ、（Ｒ２）は抵抗、（４）はアンテ
ナ同調回路、（５）は高周波増幅段、（６）はイメージ
トラップ回路である。FIG. 1 is a circuit diagram of an antenna circuit including an image trap circuit of an FM tuner according to an embodiment of the present invention.
3) is a capacitor, (L2) is a coil, (VC,) is a bevel cap, (C4) is a tuning capacitor, (C9) is a bypass capacitor, (R2) is a resistor, (4) is an antenna tuning circuit, (5) is a high frequency amplification stage, and (6) is an image trap circuit.
次に動作を説明する。Next, the operation will be explained.
コイル（Ｌ□）と同調用コンデンサ（Ｃ４）とバリキャ
ップ（ＶＣ，）とによる並列共振回路は、イメージ周波
数に同調し、その同調カーブは第２図の様になる。さら
に、この並列共振回路のインピーダンスは、充分低い純
抵抗分になり、コンデンサ（Ｃ３）も、ＦＭ周波数帯に
は充分低いインピーダンスの為、アンテナから供給され
たイメージ信号は、アンテナ端で、低インピーダンスで
アースにシャントされる。また、並列共振回路のＱは高
くとれて、アンテナ接続時にも、コンデンサ（Ｃ１）で
接続されている為、Ｑがダンプされず、負荷Ｑも高くと
れて、急峻な減衰特性を得ることができる。アンテナ端
での減水特性は、第３図の様になり、受信帯域を減衰さ
せずに、充分イメージ周波数を減衰させる％ができる。A parallel resonant circuit consisting of a coil (L□), a tuning capacitor (C4), and a varicap (VC, ) is tuned to the image frequency, and its tuning curve is as shown in FIG. Furthermore, the impedance of this parallel resonant circuit is a sufficiently low pure resistance component, and the capacitor (C3) also has a sufficiently low impedance for the FM frequency band, so the image signal supplied from the antenna is transmitted at a low impedance at the antenna end. is shunted to ground. In addition, the Q of the parallel resonant circuit is high, and even when the antenna is connected, since it is connected with a capacitor (C1), the Q is not dumped, the load Q can be kept high, and a steep attenuation characteristic can be obtained. . The water reduction characteristic at the antenna end is as shown in FIG. 3, and it is possible to sufficiently attenuate the image frequency without attenuating the reception band.
発明の効果
以１−ユ説明したように本発明によれば、並列共振回路
を用いたので、無負荷Ｑを高くとることができ、またア
ンテナ接続時にも、第２のコンデンサを通してアンテナ
に接続されているので、Ｑダンプされず、負荷Ｑも高く
とれる。したがって、イメージ周波数での減衰量を大き
くとることができて、かつ受信帯域内でのトラップ回路
挿入による減衰もないので、感度低下もおこらない。Effects of the Invention As explained in 1-U, according to the present invention, since a parallel resonant circuit is used, a high no-load Q can be achieved, and even when the antenna is connected, the antenna is connected to the antenna through the second capacitor. Therefore, the load Q can be kept high without being Q-dumped. Therefore, the amount of attenuation at the image frequency can be increased, and there is no attenuation due to the insertion of a trap circuit within the receiving band, so that sensitivity does not decrease.
第１図は本発明の一実施例におけるイメージトラップ回
路を含むＦＭチューナのアンテナ回路の回路図、第２図
は本発明の一実施例におけるイメージトラップ回路の並
列共振回路の周波数特性の説明図、第３図は同イメージ
トラップ回路のアンテナ端での減衰特性の説明図、第４
図は従来のイメージトラップ回路を含むＦＭチューナの
アンテナ回路の回路図、第５図は従来のイメージトラッ
プ回路のアンテナ端での減衰特性の説明図である。
（ＶＣ２）・・・バリキャップ、 （Ｌ２）・・・コイ
ル、（Ｃ３）・・・コンデンサ、（Ｃ４）・・・同調用
コンデンサ代理人 森 本 義 弘
第１図
第２図 第３図
第４図
第５図
；
イメージ“用３１ｉ委（FIG. 1 is a circuit diagram of an antenna circuit of an FM tuner including an image trap circuit according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of frequency characteristics of a parallel resonant circuit of an image trap circuit according to an embodiment of the present invention. Figure 3 is an explanatory diagram of the attenuation characteristics at the antenna end of the same image trap circuit.
The figure is a circuit diagram of an FM tuner antenna circuit including a conventional image trap circuit, and FIG. 5 is an explanatory diagram of attenuation characteristics at the antenna end of the conventional image trap circuit. (VC2)...varicap, (L2)...coil, (C3)...capacitor, (C4)...tuning capacitor Agent Yoshihiro MorimotoFigure 1Figure 2Figure 3 Figure 4 Figure 5; Image “31i Committee (
Claims (1)
のコンデンサとを並列接続した並列共振回路と、この並
列共振回路とアンテナ入力端との間に接続された第２の
コンデンサとを備えたＦＭチューナのイメージトラップ
回路。1. Varicap and coil as variable tuning elements and the first
An image trap circuit for an FM tuner, comprising: a parallel resonant circuit connected in parallel with a capacitor; and a second capacitor connected between the parallel resonant circuit and an antenna input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208487A JPS6187433A (en) | 1984-10-03 | 1984-10-03 | FM tuner image trap circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59208487A JPS6187433A (en) | 1984-10-03 | 1984-10-03 | FM tuner image trap circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6187433A true JPS6187433A (en) | 1986-05-02 |
Family
ID=16556975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59208487A Pending JPS6187433A (en) | 1984-10-03 | 1984-10-03 | FM tuner image trap circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187433A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114637A (en) * | 1996-03-05 | 2000-09-05 | Citizen Watch Co., Ltd. | Rocker-type manipulator for selectively operating switches mounted in liquid crystal display apparatus |
-
1984
- 1984-10-03 JP JP59208487A patent/JPS6187433A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114637A (en) * | 1996-03-05 | 2000-09-05 | Citizen Watch Co., Ltd. | Rocker-type manipulator for selectively operating switches mounted in liquid crystal display apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4295108A (en) | Filter circuit employing surface acoustic wave device | |
| US4006290A (en) | Surface wave frequency selective device | |
| US5157362A (en) | Narrow band notch filter with extended passband | |
| US4297660A (en) | Electric circuit using surface acoustic wave device | |
| US5978663A (en) | Antenna tuning circuit | |
| JP3157372B2 (en) | filter | |
| JP3136867B2 (en) | Tunable bandpass filter | |
| US4268807A (en) | Band-pass filter and gain stage | |
| JP3106513B2 (en) | Electronic tuning tuner | |
| US4633520A (en) | Prescaler input circuit | |
| JPS5937889B2 (en) | Variable attenuator circuit using PIN diode | |
| JP3091980B2 (en) | FM radio receiver | |
| JP3074990B2 (en) | Electronic tuner | |
| JPH0221798Y2 (en) | ||
| JPH03135211A (en) | Variable tuning band pass filter | |
| GB2148067A (en) | Circuitry of a filter tunable to microwave frequencies, and implementation of the same | |
| JPH04260221A (en) | Vhf input filter circuit for electronic tuner | |
| JPS6316187Y2 (en) | ||
| JPH036686B2 (en) | ||
| JP3401870B2 (en) | Trap circuit | |
| KR860001650Y1 (en) | Bit characteristic suppression circuit of TV high band | |
| JP3277527B2 (en) | Tuner | |
| JPS59188242A (en) | frequency conversion circuit | |
| JPS6145655Y2 (en) | ||
| JPS63313986A (en) | CATV converter tuner input filter circuit |