JPS6188445U - - Google Patents

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Publication number
JPS6188445U
JPS6188445U JP16984584U JP16984584U JPS6188445U JP S6188445 U JPS6188445 U JP S6188445U JP 16984584 U JP16984584 U JP 16984584U JP 16984584 U JP16984584 U JP 16984584U JP S6188445 U JPS6188445 U JP S6188445U
Authority
JP
Japan
Prior art keywords
power input
interference wave
capacitor
circuit
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16984584U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16984584U priority Critical patent/JPS6188445U/ja
Publication of JPS6188445U publication Critical patent/JPS6188445U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による妨害波除去回路の一実施
例の構成を示した回路図、第2図は従来の妨害波
除去回路の構成を示した回路図、第3図は第1図
及び第2図に示した回路を使用したときの妨害波
強度の周波特性図である。 C〜C…コンデンサ、1…本考案の回路に
おける妨害波強度、2…従来の回路における妨害
波強度、3…FCC規制クラスBの伝導雑音許容
値。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of the interference wave removal circuit according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a conventional interference wave removal circuit, and FIG. FIG. 2 is a frequency characteristic diagram of interference wave intensity when the circuit shown in FIG. 2 is used. C1 to C4 ... Capacitor, 1... Interference wave intensity in the circuit of the present invention, 2... Interference wave intensity in the conventional circuit, 3... Conducted noise tolerance value of FCC regulation class B.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流及び直流の電源入力を2系統以上保有する
電源回路において、直流側アース線とすべての電
源入力線間にコンデンサを挿入接続することを特
徴とする妨害波除去回路。
An interference wave removal circuit characterized in that, in a power supply circuit having two or more AC and DC power input systems, a capacitor is inserted and connected between a DC side ground wire and all power input lines.
JP16984584U 1984-11-10 1984-11-10 Pending JPS6188445U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16984584U JPS6188445U (en) 1984-11-10 1984-11-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16984584U JPS6188445U (en) 1984-11-10 1984-11-10

Publications (1)

Publication Number Publication Date
JPS6188445U true JPS6188445U (en) 1986-06-09

Family

ID=30727558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16984584U Pending JPS6188445U (en) 1984-11-10 1984-11-10

Country Status (1)

Country Link
JP (1) JPS6188445U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154327A (en) * 1982-03-05 1983-09-13 ソニー株式会社 Unnecessary raditation preventing device for switching power source circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58154327A (en) * 1982-03-05 1983-09-13 ソニー株式会社 Unnecessary raditation preventing device for switching power source circuit

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