JPS6188542A - Formation of multilayer interconnection of semiconductor element - Google Patents
Formation of multilayer interconnection of semiconductor elementInfo
- Publication number
- JPS6188542A JPS6188542A JP20966984A JP20966984A JPS6188542A JP S6188542 A JPS6188542 A JP S6188542A JP 20966984 A JP20966984 A JP 20966984A JP 20966984 A JP20966984 A JP 20966984A JP S6188542 A JPS6188542 A JP S6188542A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- wiring layer
- wiring
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 229920001721 polyimide Polymers 0.000 claims abstract description 8
- 239000009719 polyimide resin Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000011109 contamination Methods 0.000 abstract description 2
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 241000272201 Columbiformes Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- LNOPIUAQISRISI-UHFFFAOYSA-N n'-hydroxy-2-propan-2-ylsulfonylethanimidamide Chemical compound CC(C)S(=O)(=O)CC(N)=NO LNOPIUAQISRISI-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体素子の多層配線形成方法に係り、特に
酸素プラズマでエツチングできる層間絶縁膜を用いた多
層配線ＩＭ造の形成方法に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for forming multilayer wiring for semiconductor devices, and particularly relates to a method for forming multilayer wiring IM using an interlayer insulating film that can be etched with oxygen plasma. .
（従来の技術）
従来、酸素プラズマでエツチングする層間絶縁膜（例え
ばポリイミド樹脂膜）を用いた多層配線構造の形成にお
いては、ス／Ｌ−ホールパターニックにおけるエツチン
グマスクの選択がテＩｔ ｌ、かった。(Prior Art) Conventionally, in the formation of a multilayer wiring structure using an interlayer insulating film (for example, a polyimide resin film) that is etched with oxygen plasma, the selection of an etching mask for S/L-hole patterning has been difficult. Ta.
なぜなら、エツチングを酸素プラズマで行うため、通常
エツチングマスクとして用いられる有機系士トレジスト
は、耐酸素プラズマ性がないため、今後、ますます高精
度・微細化が要求されろバターニングプロセスにおいて
は、使用することができない。This is because etching is performed using oxygen plasma, and the organic photoresists normally used as etching masks are not resistant to oxygen plasma, so they cannot be used in the patterning process, which will require increasingly high precision and fineness in the future. Can not do it.
そこで、Ｅｘｔｅｎｄｅｄ Ａｂｓｔｒａｃｔ （１９
８３Ｆａｌｌｌ Ｐ３４１ （第１の文献）およびＩ
ＢＭＴｅｃｈｎｉｃａｌ Ｄｉｓｃｌｏｓｕｒｅ
Ｂｕｌｌｅｔｉｎ ２ ３［２］ （１９８０−７
１Ｐ２Ｓ５ （第２の文献ン１ζ示すれるように、レジ
ストと、／ｌ絶１！膜の間ニ、耐酸素プラズマ性の中１
）１Ｊ膜（上記第１の文献ではＣＶＤ ５ｉｎ２膜、上
記第２の文献ではＴ１膜）を形成し、まず、最上層のレ
ジスト膜を通常のホトリソ工程を用いてパターニングし
、次に、中間膜を、レジストをエツチングマスクとして
パターニングし、さらに、層間絶縁膜を、中間膜をエツ
チングマスクとして酸素プラズマによりパターニングす
るという方法が主に取られている。Therefore, Extended Abstract (19
83Fall P341 (first document) and I
BMTechnical Disclosure
Bulletin 2 3 [2] (1980-7
1P2S5 (As shown in the second document, between the resist and the /l film, the oxygen plasma resistance is 1
) 1J film (CVD 5in2 film in the above-mentioned first document, T1 film in the above-mentioned second document), first, the uppermost resist film is patterned using a normal photolithography process, and then the intermediate film is formed. The main method used is to pattern the interlayer insulating film using a resist as an etching mask, and then pattern the interlayer insulating film using oxygen plasma using an intermediate film as an etching mask.
（発明が解決しようとする問題点）
しかし、このような方法では、中間膜の形成・パターニ
ング・除去といった工程が加わって、プロセスが複雑に
なるばかりでなく、中間膜を除去する際に、スルー示−
ル底面に露出している下層配置線金属や、層間絶縁膜表
面にダメージや汚染を与えてしまうという欠点があった
。(Problem to be solved by the invention) However, this method not only complicates the process by adding steps such as forming, patterning, and removing the intermediate film, but also requires a through-hole when removing the intermediate film. Show
This method has the disadvantage that it damages and contaminates the underlying wiring metal exposed at the bottom of the module and the surface of the interlayer insulating film.
（問題点を解決するための手段）
そこで、この発明では、前記中間膜として、層間絶縁膜
の上層配線材料（第１の配線層材料）あるいは上層配線
材料（第２の配線層材料）と同種の材料を用いる。(Means for Solving the Problems) Therefore, in the present invention, the intermediate film is of the same type as the upper layer wiring material (first wiring layer material) or the upper layer wiring material (second wiring layer material) of the interlayer insulating film. Use the following materials.
（作 用）
このようにすれば、中間膜を、そのまま上層配！（第２
の配線層）として用いる乙とができるため、従来技術の
ように中間膜を除去する必要がなく、そのため、中間膜
を除去する工程を省けるばかりでなく、上述したような
ダメージや汚染の心配もない。(Function) In this way, the interlayer film can be directly placed on the upper layer! (Second
This eliminates the need to remove the interlayer film as in the conventional technology, which not only eliminates the process of removing the interlayer film, but also eliminates the risk of damage and contamination as described above. do not have.
（実施例）
以下、この発明の一実施例を第１図ｆａｌなＬ）しｉｈ
ｌを８照して説明する。(Example) Hereinafter, an example of this invention will be shown in Fig. 1.
I will explain with reference to 8.
第１図ｆａｔζζおいて、１はダイオード・トランジス
タなどの回路素子が作り込まれた半導体基板であり、そ
の上に、第１層配線（第１の配線層）として５０００人
〜６０００人厚のＡｌの配線パターン２が形成されてお
り、さらに、その上に、層間絶縁膜としてポリイミド樹
脂膜３が１〜２ ）ｘｎ厚に形成されている。In FIG. A wiring pattern 2 is formed thereon, and a polyimide resin film 3 having a thickness of 1 to 2)xn is further formed thereon as an interlayer insulating film.
次に、第１図（ｂｌのように、中間膜としてＡｌ膜４を
ポリイミド樹脂膜３上に約１０００人の厚さで形成する
。Next, as shown in FIG. 1 (bl), an Al film 4 is formed as an intermediate film on the polyimide resin film 3 to a thickness of about 1000 mm.
次に、第１図（ｃｌのように、有機系ホトレジスト＠５
を０．５〜１）ｓの厚さに塗布した後、通常のホトリソ
グラフィ技術によって、第１図ｆｄｌのようζこ、有機
系ホトレジスト膜５にスルーホールノ（ターン６を形成
する。Next, as shown in Figure 1 (cl), organic photoresist@5
After coating the organic photoresist film 5 to a thickness of 0.5 to 1) seconds, through holes (turns 6) are formed in the organic photoresist film 5 as shown in FIG.
次に、有機系ホトレジスト膜５をエツチングマスクとし
て、Ａｌ膜４を、塩素系ガスプラズマＬこよってドライ
エツチングし、第１図ｔｅｌのよう（こ、Ａｌ膜４にス
ルーホールパターン（開孔部）６を転写する。Next, using the organic photoresist film 5 as an etching mask, the Al film 4 is dry etched using chlorine gas plasma L to form a through hole pattern (opening) in the Al film 4 as shown in FIG. Transfer 6.
さらに、スルーホールパターン６より、酸ｇプラズマに
よりドライエツチングを行うと、第１図（ｉｌのように
、ポリイミド樹脂Ｂ３にスルーホーノドパターン６か転
写される。同時に、有機系ホトレノスト膜５が酸素プラ
ズマにより除去さＪする。Furthermore, when the through-hole pattern 6 is dry-etched using acid G plasma, the through-hole pattern 6 is transferred to the polyimide resin B3 as shown in FIG. Removed by plasma.
次に、スルーホール底面のＡｌ酸化物除去之３よび洗浄
の目的で、スルファミン酸あるいはフッ酸の水溶液に全
体を浸漬する。この時、同時に、Ａｌ膜４の表面も、酸
化物除去および洗浄がなされる。Next, the entire structure is immersed in an aqueous solution of sulfamic acid or hydrofluoric acid for the purpose of removing Al oxide from the bottom of the through hole and cleaning. At this time, oxides are removed and the surface of the Al film 4 is also cleaned.
次に、中間膜としてのＡｔ’膜４を残したまま、その表
面上およびスルーホ−ルを含む全面に、第２層配線金属
（第２の配線層材料）としてＡｊ’膜７を１．０〜１．
５声厚に形成し、その後、通常のホトリソ・エツチング
工程により前記Ａｌｙｆ；！、７をパターニングするこ
とにより、第１図（ｇｌに示すよう ・に、残存Ａｊ膜
７からなる第２層配線パターン（第２の配線層）を形成
する。Next, while leaving the At' film 4 as an intermediate film, an Aj' film 7 of 1.0% is applied as a second layer wiring metal (second wiring layer material) on its surface and the entire surface including the through holes. ~1.
The Alyf; , 7, a second layer wiring pattern (second wiring layer) made of the remaining Aj film 7 is formed as shown in FIG. 1 (gl).
次に、鳩中あるいはＮ２中で４００〜５００℃て熱処理
を行うと、第１図（ｈｌのように、Ａｌ膜４とＡｌ膜７
が境界面で互い（こ溶けあって単一のへｌ膜Ｓとなる。Next, when heat treatment is performed at 400 to 500°C in a pigeon or N2, the Al film 4 and the Al film 7 are heated as shown in FIG.
The two melt into each other at the interface to form a single helium S.
これで、ポリイミド樹脂を層間絶縁膜とするＡ１２層配
線構造が形成されたオつけである。This completes the A12 layer wiring structure using polyimide resin as an interlayer insulating film.
（発明の効果）
以上説明したように、この発明の方法では、中間膜とし
て、下層配線材料（第１の配線層材料）あるいは上層配
線材料（第２の配線層材＄４）と同種の材料全円いたの
で、中間膜を、そのまま上層配線材料として用いること
ができる。そのため、従来技術のように中間膜を除去す
る必要がなく、中間膜を除去する工程を省（ことができ
、加えて、中間膜除去工程によるスルーホール底面や層
間絶縁膜表面のダメージや汚染を防止てきる。(Effects of the Invention) As explained above, in the method of the present invention, the intermediate film is made of the same type of material as the lower layer wiring material (first wiring layer material) or the upper layer wiring material (second wiring layer material $4). Since the entire circle was formed, the intermediate film can be used as is as an upper layer wiring material. Therefore, unlike conventional technology, there is no need to remove the intermediate film, and the process of removing the intermediate film can be omitted. It can be prevented.
第１図（ｎ）ないしくｈ）はこの発明の半導体素子の多
層配線形成方法の一実施例を工程順に示す断面図である
。
１ 半導体基板、２− Ａｌ配線パターン、３ ポリイ
ミド樹脂膜、４−Ａｌ膜、５ 有機系ホトレジスト膜、
６ スルーホールパクーノ、７．８−Ａｌ膜。
第１図FIGS. 1(n) to 1h) are cross-sectional views showing one embodiment of the method for forming multilayer wiring of a semiconductor device according to the present invention in the order of steps. 1 semiconductor substrate, 2-Al wiring pattern, 3 polyimide resin film, 4-Al film, 5 organic photoresist film,
6 Through-hole Pakuno, 7.8-Al film. Figure 1
Claims (2)
の第１の配線層上に酸素プラズマによってエッチングで
きる層間絶縁膜を設ける工程と、その層間絶縁膜上に、
前記第１の配線層材料あるいは後述する第２の配線層材
料と同種の材料による中間膜を設ける工程と、その中間
膜にホトリソ技術により開孔部を形成する工程と、その
開孔部より、酸素プラズマにより、前記層間絶縁膜にス
ルーホールを形成する工程と、そのスルーホール内およ
び前記中間膜上を含む全面に第２の配線層材料を設ける
工程と、その第２の配線層材料を、ホトリソ・エッチン
グ技術によりパターニングして第２の配線層を得る工程
とからなる半導体素子の多層配線形成方法。(1) A step of providing a first wiring layer on a semiconductor substrate, a step of providing an interlayer insulating film that can be etched by oxygen plasma on the first wiring layer, and a step of providing an interlayer insulating film that can be etched by oxygen plasma on the first wiring layer,
A step of providing an intermediate film made of the same kind of material as the first wiring layer material or a second wiring layer material to be described later, a step of forming an opening in the intermediate film by photolithography, and a step of forming an opening from the opening. A step of forming a through hole in the interlayer insulating film by oxygen plasma, a step of providing a second wiring layer material on the entire surface including inside the through hole and on the intermediate film, and a step of applying the second wiring layer material, A method for forming multilayer wiring for a semiconductor device, which comprises the step of patterning using photolithography and etching technology to obtain a second wiring layer.
、層間絶縁膜としてポリイミド樹脂を用いることを特徴
とする特許請求の範囲第１項記載の半導体素子の多層配
線形成方法。(2) The method for forming multilayer interconnects in a semiconductor device according to claim 1, characterized in that Al is used as the first and second interconnect layer materials, and polyimide resin is used as the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20966984A JPS6188542A (en) | 1984-10-08 | 1984-10-08 | Formation of multilayer interconnection of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20966984A JPS6188542A (en) | 1984-10-08 | 1984-10-08 | Formation of multilayer interconnection of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6188542A true JPS6188542A (en) | 1986-05-06 |
Family
ID=16576640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20966984A Pending JPS6188542A (en) | 1984-10-08 | 1984-10-08 | Formation of multilayer interconnection of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6188542A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373647A (en) * | 1986-09-17 | 1988-04-04 | Sanyo Electric Co Ltd | Manufacture of multilayer interconnection |
-
1984
- 1984-10-08 JP JP20966984A patent/JPS6188542A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6373647A (en) * | 1986-09-17 | 1988-04-04 | Sanyo Electric Co Ltd | Manufacture of multilayer interconnection |
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