JPS6188575A - LED array - Google Patents

LED array

Info

Publication number
JPS6188575A
JPS6188575A JP59210897A JP21089784A JPS6188575A JP S6188575 A JPS6188575 A JP S6188575A JP 59210897 A JP59210897 A JP 59210897A JP 21089784 A JP21089784 A JP 21089784A JP S6188575 A JPS6188575 A JP S6188575A
Authority
JP
Japan
Prior art keywords
type
light
layer
light emitting
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59210897A
Other languages
Japanese (ja)
Other versions
JPH0458714B2 (en
Inventor
Kazuhiro Kurata
倉田 一宏
Shoji Sumi
隅 彰二
Takeshi Takahashi
健 高橋
Toshio Sagawa
佐川 敏男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP59210897A priority Critical patent/JPS6188575A/en
Publication of JPS6188575A publication Critical patent/JPS6188575A/en
Publication of JPH0458714B2 publication Critical patent/JPH0458714B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components

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  • Led Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、光プリンタの感光ドラム照射用光源等に用い
られる変調光源としてのL E Dアレイに関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LED array as a modulated light source used as a light source for irradiating a photosensitive drum of an optical printer.

[従来の技術] 従来、光プリンタ等に用いられるL[Dアレイはいわゆ
る平面発光型のものであった。すなわち、GaAs等の
単結晶基板上にGaAS   P  等−x  x の混晶系エピタキシャル層を成長させ、このエピタキシ
ャル成長1?g内に形成した注入型発光領域から発光す
る光を前記エピタキシ1フル成長層の表面から取り出づ
゛イ1−″i造であった。
[Prior Art] Conventionally, L[D arrays used in optical printers and the like have been of the so-called plane light emitting type. That is, a mixed crystal epitaxial layer of -x x such as GaAs P is grown on a single crystal substrate such as GaAs, and this epitaxial growth 1? The structure was such that the light emitted from the injection type light emitting region formed in g was extracted from the surface of the epitaxy 1 full growth layer.

ところが、平面発光型LEDアレイは、通常幅1M当り
8個程度、最低でも4個以上の発光部を必要とするため
、発光部の直上に設けるオーミック電極のWr造が微細
になり、かつ発光領域の1のエピタキシセル成長層の混
晶比を高くして光透過性をもたせる必要もあり、充分に
接触抵抗の低いA−ミックコンタ″クトを形成すること
が固層1であった。
However, a planar light emitting type LED array usually requires about 8 light emitting parts per 1M width, and at least 4 or more light emitting parts, so the Wr structure of the ohmic electrode provided directly above the light emitting part becomes fine and the light emitting area is small. It is also necessary to increase the mixed crystal ratio of the epitaxial cell growth layer (1) to provide optical transparency, and it is necessary to form an A-mic contact with sufficiently low contact resistance in the solid layer (1).

そのため、安定した高い歩留りで素子を生産することは
容易ではなかった。ザなわら、発光部が設けられた素子
表面に大型の金属電極を形成した場合、この電極により
発光が妨げられまた微■Iイ;電極を形成した場合、各
発光部に形成された各電極の接触抵抗の差が大きくなり
、各発光部の発光強度が不均一になり易かった。
Therefore, it has not been easy to produce devices with a stable high yield. However, if a large metal electrode is formed on the surface of the element where the light-emitting part is provided, this electrode will prevent light emission, and if a small electrode is formed, each electrode formed in each light-emitting part will The difference in contact resistance becomes large, and the light emission intensity of each light emitting part tends to become non-uniform.

また、接触抵抗を4−分低くするため、電極に接触する
混晶系エピタキシャル成長層表面のエネルギ禁止帯幅を
狭くする如く混合結晶比率を低くすると、この狭い禁止
帯層が光を吸収してしまい、やはり外部への発光効率を
低下させでいた。
In addition, in order to lower the contact resistance by 4 minutes, the mixed crystal ratio is lowered by narrowing the energy forbidden band width on the surface of the mixed crystal epitaxial growth layer in contact with the electrode, and this narrow band gap layer absorbs light. However, the efficiency of emitting light to the outside was still reduced.

このようなことから、従来の平面発光型LEDアレイに
おいては、n型エピタキシャル成長層表面から7クセブ
タ不純物であ。Znを選択拡散させることによって微細
なp−型領域(寸なわち、発光領域)の列を作り、各p
−型領領域表面にそれぞれ分離した微小電極を形成させ
るのが酋通であった。このようにすれば、Zr+Kr1
l領域の表面(すなわら発光部)は少なくとも1102
0C゛3程度の高キャリア濃度となるため電極とは低接
触抵抗となるが、やはり高キャリア濃度のためZn拡散
領域での光吸収が大きくなってしまうという問題があっ
た。
For this reason, in the conventional planar light emitting type LED array, the impurity is 7 cubic centimeters from the surface of the n-type epitaxial growth layer. By selectively diffusing Zn, rows of fine p-type regions (i.e., light-emitting regions) are created, and each p-type region is
- The idea was to form separate microelectrodes on the surface of the mold region. In this way, Zr+Kr1
The surface of the l region (i.e. the light emitting part) is at least 1102
Since the carrier concentration is as high as 0 C゛3, the contact resistance with the electrode is low, but there is still a problem in that the high carrier concentration increases light absorption in the Zn diffusion region.

[R明の目的] 本発明は、前記した従来技術の問題点に鑑み、各発光領
域へ形成された電極が体接触抵抗であり、かつ、これら
電極により発光が妨げられることのないLEDアレイを
提供することを目的とする。
[Purpose of R-light] In view of the problems of the prior art described above, the present invention provides an LED array in which the electrodes formed in each light-emitting region have body contact resistance and the light emission is not hindered by these electrodes. The purpose is to provide.

[問題点を解決ザるための手段] 本発明のLEDアレイは、発光部が素子の側面に幅1 
mm当り4箇所の割合で形成されており、上記素子の表
面にオーミック電極が形成されていることを特徴とする
ものである。
[Means for solving the problem] In the LED array of the present invention, the light emitting part is formed on the side surface of the element with a width of 1
The elements are formed at a ratio of 4 points per mm, and are characterized in that ohmic electrodes are formed on the surface of the element.

「実施例コ 以下、本発明の実施例を図面に基づき訂細に説明する。"Example code" Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

実施例1 第1図は、本発明の一実施例を示ず説明図である。Example 1 FIG. 1 is an explanatory diagram that does not show one embodiment of the present invention.

n型GaAs4板1の表面にn型Ga   Af−X XAS層2.n型Ga   AIVAS層3および−y n1型GaAS層4が順次成長させられる。次に、n1
型GaAS層4の表面にフォスフA・シリケート・ガラ
ス(PSG)膜5が形成され、適宜設定された間隔をお
いて、PSGSbO2部分が半円状に除去され、そのた
め、PSGSbO2去された部分にn1型GaAS層4
に接触しかつ、互いに接触しないようなマイナス電極(
オーミック電t!Vり6がPSGSbO2にアレイ状に
形成され、半円状のオーミック接触部7が形成される。
An n-type Ga Af-X XAS layer 2 is formed on the surface of the n-type GaAs4 plate 1. An n-type Ga AIVAS layer 3 and a -yn1-type GaAS layer 4 are sequentially grown. Next, n1
A phospho-A silicate glass (PSG) film 5 is formed on the surface of the type GaAS layer 4, and the PSGSbO2 portion is removed in a semicircular manner at appropriately set intervals, so that n1 is formed in the PSGSbO2 removed portion. type GaAS layer 4
Negative electrodes (
Ohmic electric t! V holes 6 are formed in an array on the PSGSbO2, and a semicircular ohmic contact portion 7 is formed.

そして、マイナス電極6のPSGSbO2去されて露出
したnj型GaAS層に接触している部分には半円状の
くぼみ6aができる。p型GaAS基板1の裏面全体に
はプラス電極(オーミック電極)8が形成されている。
Then, a semicircular depression 6a is formed in the portion of the negative electrode 6 that is in contact with the nj-type GaAS layer exposed by removing the PSGSbO2. A positive electrode (ohmic electrode) 8 is formed on the entire back surface of the p-type GaAS substrate 1 .

このような構成の素子において、マイナス電極6とプラ
ス電8J、8との間に順方向に電圧をバイアスすると、
電流はオーミック接触部7のそれぞれに集中して流れ、
素子側面の発光部9より側方へ光が放射される。
In an element having such a configuration, when a voltage is biased in the forward direction between the negative electrode 6 and the positive electrodes 8J and 8,
The current flows concentratedly in each of the ohmic contacts 7,
Light is emitted laterally from the light emitting section 9 on the side surface of the element.

すなわち、n1型GaAS層4は、この表面にPSGS
bO2りそれぞれ分離されアレイ状に設けられたマイナ
ス電イ触6のそれぞれと挿めて接触抵抗の低いオーミッ
ク接触部7を形成してJ5つ、電子はオーミック接触部
7よりn型Ga1−xAノXAS層3を経てn型Ga 
  AI!XASIiIf72の−X 中に注入8°れ、発光部の内部で正孔と発光再結合を行
い素子側面の発光部9から光が放射されるのである。
That is, the n1 type GaAS layer 4 has PSGS on its surface.
The ohmic contacts 7 with low contact resistance are formed by inserting the bO2 into each of the negative electrode contacts 6 which are separated from each other and provided in an array. n-type Ga via XAS layer 3
AI! It is injected into -X of XASIiIf 72 by 8 degrees, undergoes radiative recombination with holes inside the light emitting part, and light is emitted from the light emitting part 9 on the side surface of the element.

オーミック接触部7の数とマイナス電極6の教は、それ
ぞれ対応して同じであるが、プリンタ用のLEI)アレ
イ等としては素子の幅1 mm当り4箇所以上にオーミ
ック接触部7を形成する必要があり、通常8箇所場合に
よっては16筒所にオーミック接触部7を形成する。な
お、オーミック接触部7の曲率半径をiot1m以下程
度にすれば、n型Ga1−xAir xAsFj2内で
の注入型発光は、同層内であまり吸収を受けずに発光部
9より側方に発光される。
The number of ohmic contact portions 7 and the structure of the negative electrode 6 are the same, but for LEI (LEI) arrays for printers, it is necessary to form ohmic contact portions 7 at four or more locations per 1 mm width of the element. Ohmic contact portions 7 are usually formed at 8 locations, but in some cases at 16 locations. Note that if the radius of curvature of the ohmic contact part 7 is set to about 1 m or less, the injection type light emission within the n-type Ga1-xAirxAsFj2 will be emitted laterally from the light-emitting part 9 without being absorbed much within the same layer. Ru.

又、n1型GaAS層4は住人型発光を透過することが
なく、かつ素子側面からの発光に対しても何ら影響がな
く、史にはマイナス電極6も光の透過部とはならないた
め、広面積な発光部9を1゛することがでさる。
Furthermore, the n1-type GaAS layer 4 does not transmit resident-type light emission and has no effect on light emission from the side of the device. It is possible to reduce the area of the light emitting section 9 to 1.

実施例2 第2図は、本発明の他の実施例を示す説明図である。Example 2 FIG. 2 is an explanatory diagram showing another embodiment of the present invention.

実施例1と同様に、p型QaΔS基板1の表面にn型G
a   Af!xAsE’42.n型Ga   t\1
−X             1−YJyAstn3
および、nt型GaAS層4が順次成長させられている
As in Example 1, n-type G is deposited on the surface of p-type QaΔS substrate 1.
a Af! xAsE'42. n-type Ga t\1
-X 1-YJyAstn3
Then, an nt-type GaAS layer 4 is successively grown.

本実施例の場合には、電流がn 型GaAS層4内全4
内するのを防ぎ、オーミック接触部7での電流密度を高
くして発光エネルギーを高めるために、オーミック接触
部7を通らないようnt型GaAS層4を貫通する深さ
でかつ発光部9を有づ゛る索子側面に平行なエツチング
1lls 10が設けられている。次に、この上にPS
G膜5が形成され、PSG膜5の一部分が半円状に除去
された後、n1型GaAS層4と接触してオーミック接
触部7が形成されるようにマイナス°市極6がアレイ状
に形成される。p型GaAS基板1の裏面には、実施例
1と同様にプラス電極8が形成されている。
In the case of this embodiment, the current is
In order to prevent the light from entering the NT-type GaAS layer 4 and to increase the current density at the ohmic contact part 7 to increase the light emission energy, the light emitting part 9 is formed at a depth that penetrates the NT-type GaAS layer 4 so as not to pass through the ohmic contact part 7. Parallel etchings 10 are provided on the sides of the cord. Then on top of this PS
After the G film 5 is formed and a part of the PSG film 5 is removed in a semicircular shape, the negative city poles 6 are formed in an array so as to contact the n1 type GaAS layer 4 and form an ohmic contact part 7. It is formed. A positive electrode 8 is formed on the back surface of the p-type GaAS substrate 1 as in the first embodiment.

従って、マイナス7fi極6とプラス電極8との間に順
方向に電圧をバイアスすると、電流は、n1型GaAS
層4全体に拡散することなく、集中してオーミック接触
部7を通って流れ、発光部9より側方に光が放Q4され
る。
Therefore, when a voltage is biased in the forward direction between the minus 7fi pole 6 and the plus electrode 8, the current flows in the n1 type GaAS
The light flows through the ohmic contact portion 7 in a concentrated manner without being diffused throughout the layer 4, and is emitted laterally from the light emitting portion 9 Q4.

又、第3図に示すように、エツチング溝10に垂直でか
つ各発光部9の間にn 型GaAS層4を貫通する深さ
の第2のエツチング溝11を設;することにより、°電
流かn 型QaAS層4内の発光部9を有する素子側面
に平行な方向に拡散するのを防ぐことができる。
Further, as shown in FIG. 3, by providing a second etching groove 11 perpendicular to the etching groove 10 and having a depth penetrating the n-type GaAS layer 4 between each light emitting part 9, the current can be reduced. Diffusion in the direction parallel to the side surface of the element having the light emitting portion 9 in the n-type QaAS layer 4 can be prevented.

従って、電流がオーミック接触部7へ集中し、発光エネ
ルギーを高めることができる。
Therefore, the current is concentrated on the ohmic contact portion 7, and the light emission energy can be increased.

なお、第2のエツチング溝11の表面にはPSG膜5だ
けが形成されでいる。
Note that only the PSG film 5 is formed on the surface of the second etching groove 11.

実施例3 第4図は、本発明のもう一つの他の実施例を示す説明図
である。
Embodiment 3 FIG. 4 is an explanatory diagram showing another embodiment of the present invention.

n型GaAS基板の上にはn型G a 1−X A I
i XAs層12.p’!jlGa1−y Affl 
yAs層13およびn1型GaAS層14が順次成長さ
れる。次にn型GaAS層14の表面から適宜設定され
た1m隔をおいてznが選択拡散され、p型拡散領域2
2が形成される。このp型拡散領域22tは、n型Ga
1− X A J X A S 層12に達つしな0よ
うにル成されている。
On the n-type GaAS substrate, there is an n-type Ga 1-X A I
i XAs layer 12. p'! jlGa1-y Affl
A yAs layer 13 and an n1 type GaAS layer 14 are sequentially grown. Next, zn is selectively diffused at an appropriately set distance of 1 m from the surface of the n-type GaAS layer 14, and the p-type diffusion region 2
2 is formed. This p-type diffusion region 22t is composed of n-type Ga
1-XAJXAS layer 12.

次に、n型GaAS層14の表面にp型拡j攻領域22
の1つおぎにL字型のマイナス電極16が形成され、P
SG膜15が図において横方向に連続して形成された後
、マイナス電極16が形成されていないp型拡散領[2
2に接触するようマイナス電極26がPSGil 5の
上に形成される。
Next, a p-type extended region 22 is formed on the surface of the n-type GaAS layer 14.
An L-shaped negative electrode 16 is formed at one end of the P
After the SG film 15 is formed continuously in the horizontal direction in the figure, the p-type diffusion region [2] where the negative electrode 16 is not formed is formed.
A negative electrode 26 is formed on top of PSGil 5 to contact PSGil 2 .

このような2段描造のマイナス電極とすることにより、
電極面積を広くすることができ、ワイヤボーンディング
を容易にすることができる。
By using such a two-stage negative electrode,
The electrode area can be increased and wire bonding can be facilitated.

更に、マイナス71Hffi16,26が接触している
p型拡散領域22し、キャリヤ温度が高く接触抵抗を低
くすることが容易なばかりでなく、n型GaAS基板1
の裏面に形成されたプラス電極8からの電子流の集中も
良好となり、注入発光は、p型拡散領域22直下で起こ
り、発光部1つから光が放射される。
Furthermore, the p-type diffusion region 22 with which the negative 71Hffi 16 and 26 are in contact not only has a high carrier temperature and can easily lower the contact resistance, but also has a high carrier temperature.
The concentration of the electron flow from the positive electrode 8 formed on the back surface of the p-type diffusion region 22 is also improved, and injection light emission occurs directly under the p-type diffusion region 22, and light is emitted from one light-emitting portion.

又、このような絶縁膜を介しての多層配線を用いれば、
マイナス電極は前後に3段以上に亘って更に広面積で配
線することも可能である。
Moreover, if multilayer wiring is used through such an insulating film,
It is also possible to wire the negative electrodes in three or more stages over a wider area.

なお、上記諸実絶倒にd5いては、置板結晶としてGa
As、エピタキシャル層としてGaAfASを用いて説
明したが、伯の半導体材料を用いても本発明の実施は可
能である。
In addition, in the case of d5, Ga is used as a plate crystal.
Although the description has been made using As and GaAfAS as the epitaxial layer, it is also possible to implement the present invention using other semiconductor materials.

又、p−n接合およびヘテロ接合の形成方法あるいは、
これらによって形成される発光再結合領域の分ば]方法
などは、上記実施例以外の方法を用いても本発明の実施
は可能であり、要は、電ね(やオーミック接触用狭エネ
ルギー幅層等か形成されていない素子側面から光を放出
するものならばよい。
Also, a method for forming a p-n junction and a heterojunction, or
The present invention can be implemented using methods other than the above-mentioned embodiments, such as the method for forming the radiative recombination region formed by these methods. Any device may be used as long as it emits light from the side surface of the element on which no surface is formed.

[発明の効!l!1 以上に説明した如く、本発明のLEDアレイであれば次
の様な顕著な効果を奏する。
[Efficacy of invention! l! 1. As explained above, the LED array of the present invention provides the following remarkable effects.

(1)発光部が素子側面にあるため、電極により発光が
妨げられることがなく、電極およびオーミック接触層に
光取り出し用の窓を必要としない発光密度の高いLED
アレイを1!Iることができる。
(1) Since the light emitting part is on the side of the element, light emission is not obstructed by electrodes, and LEDs with high light emission density do not require windows for light extraction in the electrodes and ohmic contact layer.
1 array! I can.

(2)電極およびオーミック接触を形成し易い高ドープ
狭いエネルギー禁止帯幅層の存在しない素子側面から光
を取り出りことができるため、電流およびA−ミック接
触層の設h1自由度が大さ゛く、低接触抵抗の電極を形
成することがでできる。
(2) Since light can be extracted from the side of the device where there is no highly doped narrow energy bandgap layer that easily forms electrodes and ohmic contacts, there is a large degree of freedom in the design of current and A-mic contact layers. , it is possible to form electrodes with low contact resistance.

(3)電極形成プロセスと発光部の形成プロセスとが無
関係であるため、電極形成プロセスが多数の発光点の発
光強度不均一性の原因になることが少なく、高歩留りで
LEDアレイを製造することができる。
(3) Since the electrode formation process and the light emitting part formation process are unrelated, the electrode formation process is less likely to cause non-uniformity in the light emission intensity of a large number of light emission points, and the LED array can be manufactured with high yield. I can do it.

(4)発光部が微細なため、素子側面発光ではあるもの
の光吸収が少ない。
(4) Since the light emitting part is minute, light absorption is low even though the light is emitted from the side of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図波歪第4図は本発明の実施例を示す説明図である
。 1・・・p型GaAS基板。 2 ・・O型G a 1−X A flX A S層。 3−n型Ga1−y Aに1yAs層。 4.14・n’型GaAS)ffl。 5.15・・・PSG膜。 6.16.26・・・マイナス電極。 7・・・オーミック接触部、8・・・プラス電極。 9.19・・・発光部。 10・・・(第1の)エツチング溝。 11・・・第2のエツチング溝。 12−n型Ga1.Aに1XAS層。 13 ・D型Ga   Af VAs層。 −Y 21 ・n型GaAs1板。 22・・・p型拡散領域 苑 1121 7; オーミ、711匝部 8ニア°ラス雷4を 飛1発発光 光 2 口
FIG. 1 shows wave distortion. FIG. 4 is an explanatory diagram showing an embodiment of the present invention. 1...p-type GaAS substrate. 2...O-type G a 1-X A flX A S layer. 3-1yAs layer on n-type Ga1-yA. 4.14 n' type GaAS) ffl. 5.15...PSG film. 6.16.26... Negative electrode. 7... Ohmic contact part, 8... Positive electrode. 9.19... Light emitting part. 10... (first) etching groove. 11...Second etching groove. 12-n-type Ga1. 1XAS layer on A. 13 ・D-type Ga Af VAs layer. -Y 21 ・N-type GaAs1 plate. 22...p-type diffusion area garden 1121 7; Omi, 711 tsubo 8 near 4 lightning strikes 4, 1 light emitting light 2 mouths

Claims (1)

【特許請求の範囲】[Claims] (1)発光部が素子の側面に幅1mm当り少なくとも4
箇所の割合で形成されており、前記素子の表面にオーミ
ック電極が形成されていることを特徴とするLEDアレ
イ。
(1) At least 4 light emitting parts per 1 mm width on the side of the element.
1. An LED array characterized in that the LED array is formed in a plurality of locations, and an ohmic electrode is formed on the surface of the element.
JP59210897A 1984-10-08 1984-10-08 LED array Granted JPS6188575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59210897A JPS6188575A (en) 1984-10-08 1984-10-08 LED array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59210897A JPS6188575A (en) 1984-10-08 1984-10-08 LED array

Publications (2)

Publication Number Publication Date
JPS6188575A true JPS6188575A (en) 1986-05-06
JPH0458714B2 JPH0458714B2 (en) 1992-09-18

Family

ID=16596887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59210897A Granted JPS6188575A (en) 1984-10-08 1984-10-08 LED array

Country Status (1)

Country Link
JP (1) JPS6188575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62162857U (en) * 1986-04-02 1987-10-16

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366864B1 (en) 1999-05-05 2002-04-02 General Electric Company Adaptive sampling rate based on power system frequency

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58131779A (en) * 1982-02-01 1983-08-05 Ricoh Co Ltd Manufacture of light-emitting diode array
JPS58170058A (en) * 1982-03-31 1983-10-06 Fujitsu Ltd Photointegrated semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58131779A (en) * 1982-02-01 1983-08-05 Ricoh Co Ltd Manufacture of light-emitting diode array
JPS58170058A (en) * 1982-03-31 1983-10-06 Fujitsu Ltd Photointegrated semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62162857U (en) * 1986-04-02 1987-10-16

Also Published As

Publication number Publication date
JPH0458714B2 (en) 1992-09-18

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