JPS618892U - electronic clock - Google Patents

electronic clock

Info

Publication number
JPS618892U
JPS618892U JP9252484U JP9252484U JPS618892U JP S618892 U JPS618892 U JP S618892U JP 9252484 U JP9252484 U JP 9252484U JP 9252484 U JP9252484 U JP 9252484U JP S618892 U JPS618892 U JP S618892U
Authority
JP
Japan
Prior art keywords
frequency
oscillation
control means
clock signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9252484U
Other languages
Japanese (ja)
Inventor
和充 小坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9252484U priority Critical patent/JPS618892U/en
Publication of JPS618892U publication Critical patent/JPS618892U/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示す電子時計の回路構成図
である。 1・・・発振器、Cc1 g Cc2・・・調整用コン
デンサ、2・・・分周回路、3・・・“計時計数カウン
タ、AC・・・オールクリア端子、T・・・テスト端子
、,14〜16・・・遅延形フリツプフロツプ、21・
・・進み修正回路、22・・・遅れ修正回路。
The drawing is a circuit diagram of an electronic timepiece showing an embodiment of this invention. 1... Oscillator, Cc1 g Cc2... Adjustment capacitor, 2... Frequency dividing circuit, 3... Clock counter, AC... All clear terminal, T... Test terminal,, 14-16... Delayed flip-flop, 21.
...Advance correction circuit, 22...Delay correction circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 発振周波数調整部を備えた発振回路と、この発振回路か
ら発振出力された基準周波数信号を所定周波数の刻時ク
ロツク信号に分周する分周回路と、この分周回路から出
力される刻時クロツク信号の周波数をデジタル的に微調
整する周波数制御手段と、外部スイッチの操作状態に応
じて前記周波数制御手段に動作指令を与える手段とを具
備したことを特徴とする電子時計。
An oscillation circuit equipped with an oscillation frequency adjustment section, a frequency division circuit that divides the reference frequency signal oscillated and output from the oscillation circuit into a clock signal of a predetermined frequency, and a clock signal output from the frequency division circuit. 1. An electronic timepiece comprising: frequency control means for digitally finely adjusting the frequency of a signal; and means for giving an operation command to the frequency control means in accordance with the operating state of an external switch.
JP9252484U 1984-06-22 1984-06-22 electronic clock Pending JPS618892U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9252484U JPS618892U (en) 1984-06-22 1984-06-22 electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9252484U JPS618892U (en) 1984-06-22 1984-06-22 electronic clock

Publications (1)

Publication Number Publication Date
JPS618892U true JPS618892U (en) 1986-01-20

Family

ID=30649395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9252484U Pending JPS618892U (en) 1984-06-22 1984-06-22 electronic clock

Country Status (1)

Country Link
JP (1) JPS618892U (en)

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