JPS618940A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive uniformity of characteristics of elements by forming the second semiconductor layer on a back surface of the semiconductor substrate which is made thin by removing the back surface after forming grooves on a surface of a semiconductor substrate and covering the substrate with an insulating film. CONSTITUTION:After a front surface of an N<+> Si substrate 21 is etched to form a groove 22, the first oxide film 23 is formed and then a polysilicon layer 24 is formed to fill said groove 22. Next, a back surface of the N<+> Si layer 21 is ground away gradually and the first oxide film 23 which is formed at the bottom of the groove 22 is exposed to form an island-shaped N<+> layer 21'. On the ground plane of N<+> layer 21, an N type Si layer 25 is formed and then the thin second oxide film 26 and a nitride film 27 are formed on said layer 25, after which apertures 28 are arranged on them. Subsequently, the N type Si layer 25 is oxidized by thermal oxidation and the third oxide film 29 for element isolation whose lower end is in contact with the first oxide film 23 which is formed at the bottom of the groove 22 is formed. Consequently, the N type Si layer 25 becomes an island-shaped N type element forming region 25' thereby facilitating the control of a thickness of said region 25'.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a method for manufacturing a semiconductor device.

(Prior Art) Conventionally, as a method for separating semiconductor integrated circuits and elements, a method using a pn junction of a semiconductor and a method using an insulator have been used.In particular, in the latter method, 1
Since the isolation region is narrow, it is suitable for high integration, and has advantages such as small parasitic capacitance and no parasitic transistors.

Next, a method for manufacturing a semiconductor device using an insulator separation method will be described with reference to the drawings.

FIGS. 1(a) to 1(a) are cross-sectional views for explaining an example of a conventional method for manufacturing a semiconductor device using an insulator separation method.

First, as shown in FIG. 1(a), an n-type impurity is diffused into the surface of an n-type silicon substrate 1 to form an n-diffusion layer 2 having a thickness of about 10 μm.

Next, as shown in FIG. 1(b), grooves 3 having a depth of about 20 μm are formed on the surface of the silicon substrate 1 by etching, and then the entire surface is oxidized to form a five-separation oxide film 4.

Next, as shown in FIG. 1(C), a p-type silicon layer 5 with a thickness of about 300 μm is formed on the entire surface of the isolation oxide film 4, and the grooves 3 are
Next, as shown in FIG. 1(d), the back surface of the silicon substrate 1 is gradually ground to expose the isolation oxide film 4 formed at the bottom of the groove 3 and form an island-shaped n-type element formation region 1. ′ is formed.

Next, as shown in FIG. 1(e), K, 1m type element formation region 1
p-type impurity and n-type impurity are introduced into p-type region 6
Then, an n+ type region 7 is provided to form circuit elements, such as a transistor formation region 8 and a resistance formation region 9. Then, the surface is covered with an oxide film 10 at the zeroth order (FIG. 1(f)) K
As shown, after openings are formed in the oxide film 10 on each impurity introduction region, AJ is deposited and etched to form the F)kl wiring 11.

In the semiconductor device manufactured in this manner, the circuit elements are completely separated by the isolation oxide film 4, so that large parasitic capacitances are not formed as in the case of isolation by pn junctions, and there is no risk of cosmic rays etc. However, the n-type element formation region 1' and the first diffusion layer 2, which are surrounded by the isolation oxide film 4 and become an island-shaped element formation region, are shown in FIGS. 1(a) and (b). As shown in FIG.
′ has the disadvantage that it is difficult to control the thickness. That is, the thickness of the n-type element forming region 1' is mainly determined by the thickness of the n++ diffused layer 2 and the depth of #I3, but the 9n diffused layer 2 is spread due to thermal cycles in the post-process. As a result, the thickness of the n-type element forming region 1' is narrowed, resulting in poor reproducibility and non-uniform characteristics of multiple formed elements.

The thickness of the n-type element forming region 1' also changes depending on the concentration of the n-type impurity introduced into the n++ diffusion layer 2. When the concentration is high, the diffusion layer 2 spreads more rapidly, so that it becomes thinner than the thickness of the n-type element forming region 1'.

If the n-type element forming region 1' is thin, the junction capacitance with the circuit element to be formed will increase and the circuit speed will be slow; if it is thick, the collector saturation resistance of the transistor will be high. , the speed of the circuit slows down and the circuit stops working properly).

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing a semiconductor device with uniform element characteristics. a step of forming a first semiconductor layer on the insulating film, a step of removing the back side of the semiconductor substrate to make the substrate thinner, and a step of forming a first semiconductor layer on the insulating film; forming a second semiconductor layer on the back surface of the semiconductor substrate, and forming an insulating layer that extends through the second semiconductor layer and connects to the insulating film at the bottom of the trench to separate the second semiconductor layer into islands. The process includes the steps of:

[Explanation of Examples]

``Next, one embodiment of the present invention will be explained using an embodiment and with reference to the drawings.

FIGS. 2(a) to (g) are process cross-sectional views for explaining one embodiment of the present invention. First, as shown in FIG. 2(a), the surface of the %nn star-shaped silicon substrate 210 is etched. After forming a groove 22 with a depth of approximately 5 μm, the entire surface is oxidized to form a first oxide film 23 for element isolation with a thickness of 1 to 3 μm.

Next, as shown in FIG. 2(b), a polysilicon layer 24 with a thickness of 300 to 500 μm is formed on the first oxide film 23 by CVD.
Polymerization is performed using a method etc. to fill in #I22.

Next, as shown in FIG. 2(c), the n-type silicon substrate 21
A first groove formed at the bottom of the groove 22 by gradually grinding the back surface of the groove 22
By exposing the first oxide film 23, an island-shaped single layer 21 surrounded by the first oxide film 23 is formed.In addition, when the oxide film 23 is not exposed, as shown in FIG. In the process, the n+ layer 21' is separated into islands.

It is also possible to form the n-type silicon substrate 21'a by treating the n-type silicon substrate according to the steps of FIGS. 1(a) to 1(c) and then introducing n-type impurities.

Next, as shown in FIG. 2(d)K, an NG silicon layer 25 made of single crystal and having a thickness of 2 to 5 μm is formed on the ground surface of the first layer 21 by epitaxial technology.

Next, as shown in FIG. 2(e), a 4C% n-type silicon layer 25
After forming a thin second oxide film 26 and a thin nitride film 27 thereon, openings 28 are selectively provided in the second oxide film 26 and nitride film 27. Next, the thin n-type silicon layer 25 is oxidized by thermal oxidation using the nitride film 27 as a mask, and the lower end of the oxide film is connected to the first oxide film 22 formed on the bottom of the $ 22 for element isolation. A third oxide film 29 is formed. Formation of this third oxide film 29 KJ:, 9n type silicon layer 25
becomes an island-shaped n-type element forming region 25'. Next, as shown in FIG.
A type impurity and an n-type impurity are introduced, a p-type region 6 and an n-type region 7 are provided, and a transistor forming region 8 and a resistor forming region 9 are formed. Then, the surface is covered with a fourth oxide film 30. Next, as shown in FIG. ◇In the semiconductor device manufactured in this way, the n-type element forming region 25' is not formed at the same time as the n layer 21' as in the conventional method, but is formed in an intermediate step, that is, in the It is formed in the process shown in FIG. 2(d). Therefore, the influence of diffusion of n-type impurities from the n-type layer 21' due to thermal cycles in subsequent steps is reduced, and the thickness of the "type element forming region 25' can be easily controlled. Therefore, The characteristics of elements such as transistors formed in the n-type element forming region 25' are uniform and have good reproducibility.

Furthermore, since the oxide film for element isolation is formed by the first and third oxide films 23 and 29, the first oxide film 2
The depth of the groove 22 covered by the groove 3 is less than 1/2 that of the conventional case (groove 3 in Fig. 1), and the isolation region (area where no element can be formed), which is approximately proportional to the width of the groove, is smaller than that of the conventional case (groove 3 in Fig. 1). 1/
It will be as small as about 2. Therefore, a semiconductor device with an improved degree of integration can be manufactured.

In the above embodiment, the shape of the groove was explained using a drawing in which the groove had a V-shaped structure, but a U-shaped structure could also be used.Also, an oxide film was used as the insulating film, but a nitride film was used as the insulating film. An insulating film such as chemical film may also be used.
[H [Effects of the Invention] As explained in detail above, according to the present invention, a method for manufacturing a semiconductor device with uniform element characteristics and improved reliability can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1) are cross-sectional views for explaining an example of a conventional method for manufacturing a semiconductor device, and FIGS. 2(a) to [g) are cross-sectional views for explaining an embodiment of the present invention. The figure is 01...
... N-type silicon substrate, 2 ... N+ diffusion layer, 3 ... Groove, 4 ... Isolation oxide film, 5.
...p-type silicon layer, -6...p-type region, 7...n-type region, 8...transistor region, 9...・Resistance area, 10...
Oxide film, 11...kl wiring, 21...
n+ type silicon substrate, 22...groove, 23...
...first oxide film, 24...polysilicon 1
25...N-type silicon L26...Second
oxide film, 27... nitride film, 28...
Opening portion, 29...Third oxide film, 30...
...Fourth oxide film O Fig. 1 Fig. 1 Fig. 2

Claims (1)

[Claims] A step of forming a groove on the surface of a semiconductor substrate and then covering the surface with an insulating film, a step of forming a first semiconductor layer on the insulating film, and a step of removing the back side of the semiconductor substrate to make the substrate thinner. forming a second semiconductor layer on the back surface of the thinned semiconductor substrate; and connecting the second semiconductor layer to the insulating film at the bottom of the trench to separate the second semiconductor layer into islands. 1. A method of manufacturing a semiconductor device, comprising: forming an insulating layer.