JPS6190308U - - Google Patents
Info
- Publication number
- JPS6190308U JPS6190308U JP17555984U JP17555984U JPS6190308U JP S6190308 U JPS6190308 U JP S6190308U JP 17555984 U JP17555984 U JP 17555984U JP 17555984 U JP17555984 U JP 17555984U JP S6190308 U JPS6190308 U JP S6190308U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- bias point
- diode
- anode
- communicates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Amplifiers (AREA)
Description
第１図は本考案に係る振幅制限回路を示す図、
第２図は従来の振幅制限回路を示す図、第３図は
ダイオードの順方向電圧対順方向電流を示す図、
第４図は本考案に係る他の振幅制限回路を示す図
である。
図中、Ｈ…受波器、Ｒ１〜Ｒ６…抵抗器、Ｄ１
〜Ｄ６…ダイオード、Ｄ７，Ｄ８…ツエナーダイ
オード、Ａ…増幅器。
FIG. 1 is a diagram showing an amplitude limiting circuit according to the present invention,
Fig. 2 is a diagram showing a conventional amplitude limiting circuit, Fig. 3 is a diagram showing forward voltage versus forward current of a diode,
FIG. 4 is a diagram showing another amplitude limiting circuit according to the present invention. In the figure, H...Receiver, R1-R6...Resistor, D1
~D6...Diode, D7, D8...Zener diode, A...Amplifier.
Claims (1)
第２端子とする平衡信号回路に正の第１バイアス
点と負の第２バイアス点を設け、前記第１端子と
第１バイアス点との間に第１のダイオードを第１
端子がアノードに連通するように接続し、前記第
２端子と第１バイアス点との間に第２のダイオー
ドを第２端子がアノードに連通するように接続し
、前記第１端子と第２バイアス点との間に第３の
ダイオードを第２バイアス点がアノードに連通す
るように接続し、さらに前記第２端子と第２バイ
アス点Ｄの間に第４のダイオードを第２のバイア
ス点がアノードに連通するように接続したことを
特徴とする振幅制限回路。 A positive first bias point and a negative second bias point are provided in a balanced signal circuit in which one input terminal is a first terminal and the other input terminal is a second terminal, and the first terminal and the first bias point are connected to each other. The first diode is connected between the first diode and the first diode.
A second diode is connected between the second terminal and a first bias point so that the second terminal communicates with the anode, and a second diode is connected between the first terminal and the second bias point. A third diode is connected between the second terminal and the second bias point D so that the second bias point communicates with the anode, and a fourth diode is connected between the second terminal and the second bias point D so that the second bias point communicates with the anode. An amplitude limiting circuit characterized in that the circuit is connected so as to communicate with the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17555984U JPS6190308U (en) | 1984-11-19 | 1984-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17555984U JPS6190308U (en) | 1984-11-19 | 1984-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6190308U true JPS6190308U (en) | 1986-06-12 |
Family
ID=30733161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17555984U Pending JPS6190308U (en) | 1984-11-19 | 1984-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190308U (en) |
-
1984
- 1984-11-19 JP JP17555984U patent/JPS6190308U/ja active Pending
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