JPS6192046A - Radio selective call receiver capable of receiving message corresponding to multi-address - Google Patents

Abstract

PURPOSE:To register, change, and to delete common addresses by providing a means which decodes contents of a message following a preliminarily deter mined code in a preliminarily determined form in accordance with the code. CONSTITUTION:When a radio frequency comes, a reception signal is detected. If a receiver has a corresponding individual selective call number ID, a voltage is applied to the receiver in response to the detection pulse. When a following frame synchronizing signal SC is detected (DT2), contents of a P-ROM50 where ID of the receiver itself and the reception signal are compared and collated with each other, and a message signal is processed by a processing part 60 of message data MD when the coincidence between them is confirmed (DT3). Message data is decoded by a decoder, and an incorporated calendar is corrected by month and day information of a pattern of a signal TS indicating month and day information of a control signal I1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio selective calling receiver, and particularly to a receiver having a multi-address message receiving function.

[Prior art]

In recent years, with the development of integrated technology, there has been a remarkable improvement in the functionality of wireless selective calling receivers, from the traditional calling-only function to ones that can even receive a series of messages consisting of numbers, letters, and symbols. .

On the other hand, in a paging service company, by adding a message transmission function, two stock price information and various product transaction information services can be considered as services that effectively utilize the immediacy of the system.

Margin below [Problem that the invention seeks to solve] What are the problems with providing these services?

Due to the nature of addresses assigned to each company or each product (hereinafter referred to as common addresses), the number of registrations and changes to users may be deleted very frequently.

Therefore, if a service company were to register, change, or cancel a common address, the user would have to go to the service company each time, resulting in cine mail. On the other hand, in addition to the complexity of counter operations at service companies, if a user who has registered on a monthly basis unilaterally fails to pay the service fee, the base station can cancel an individual address.

It is not possible to stop the service for a common address because it would cause inconvenience to other legitimate users, and it is also not possible to change the correspondence between the numbers of the common address, so it is necessary to deal with it individually, which is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks and to provide a wireless selective calling receiver with a message function that allows registration, modification, and deletion of common addresses using predetermined codes.

[Failure to solve the problem]

According to the invention, at least a frame synchronization signal.

When receiving a call signal consisting of a selective call signal, a control signal, and a message signal in this order, the content of the subsequent message is set in a predetermined format corresponding to the code in accordance with a predetermined code of the control signal. It is possible to provide a wireless selective calling receiver with a message equipped with means for decoding the message and registering or changing it in the receiver as a common address.

[Embodiments of the invention]

The present invention will be described in detail below using two drawings.

1 and 3 are block diagrams of a receiver provided in the present invention. An overview of the operation of this receiver will be explained using FIGS. 1, 4, and 5.

That is, in the switching circuit 1, (
The voltage waveform shown in j) is transmitted to the wireless section 20. A state in which power is applied intermittently to the waveform shaping 30 to ensure efficient operation of the power supply (this operation is generally referred to as battery cellping, and hereinafter referred to as rB
When a desired radio frequency arrives when a voltage is applied at the antenna 10. Radio section 20. A received signal as shown in (,) of FIG. 5A (1) is detected via the waveform shaping circuit 30. Here, the receiver's individual selection calling number (hereinafter referred to as rIDJ) "AI"
If the receiver of.

When a preamble signal (hereinafter referred to as "P") for BS cancellation is detected by the decoder 40 (DTI).

B and S are released, and voltage is continuously applied to the wireless section (j). When the subsequent frame synchronization signal (hereinafter referred to as rscJ) is detected (DT2), the program 1'-y muffler in which the own machine's ID is written is
Read-only memory (P-ROM) 50
The content of the message and the received signal are compared and verified.

When a match is confirmed (DT3), the message data (hereinafter referred to as rMDJ) processing section 60 processes the message signal following the ID signal. and the signal (d
), the content of the message data received by the signal (c) is displayed on the liquid crystal display device [LCIPJ] 90, or the signal (g) ) is output to terminal 5. Here, a central processing unit [CP
Since a voltage of 2 V or more is normally required to drive an LCD using a dynamic drive method, a booster circuit 7 is used to boost the voltage of the battery 6.

Now, each component p, sc of the above-mentioned received signal (,).

Details of the ID and MD are shown in FIG.

The Noriamp signal P is as shown in [■] in the same figure.

The frame synchronization signal SC is a repeating turn of logic "1" and "0", and the frame synchronization signal SC is a specific turn shown in the figure (ID). In the configuration shown in FIG. 3, the MSB (identification bit) has an intersymbol distance of 5 and the MSB (identification bit) is logic "0" (31).

21) code, and the message data MD has the structure shown in the same figure (I[l), MSB (
(identification bit) is given by a logical pass 1'', as shown in FIG.
.

As shown in A (If), the first control signal "T"
.

The first control signal is divided into a second control signal II'' and an information message M. That is, the first control signal shown in [■] in FIG.

(1) If there is a message addressed to your own machine, press "P1".

Code Z as message information shown as 0” if not available
With O.

(11) Information specifying the format of the following message (for example, "o o i" if the message is numerical information composed of BCD code, "oio" if the message is compatible with ASCII code, "1" if it is compatible with JIS code)
00'.

Also, if it is facsimile information, code Z1 as '111'' etc.).

(iii) Figure 5A <1. ), the first
It consists of a BCD code code -z5 representing the number of words when 31 bits are one word, as duration information specifying the time from the control signal to the next SC, T, or I. The second control signal shown in [■] in FIG. 4 includes a signal "MC8" for specifying the processing of the received message, and a signal "TS" representing time or month/day information.
”.

Here, the meaning of Table 1, which defines the message processing process corresponding to the MCS pattern, is as follows. First, item 1 means that no processing is performed on the received message. Items 2 and 3 indicate setting the rD corresponding to the received message as the ID of the device itself, or conversely changing the ID registered in the device itself. Item 4 sets the built-in clock to the time corresponding to the received message and sounds a call alarm.

“Item 5 allocates a memory area for the message memory area according to the ID and byte information corresponding to the received message.

The receiver receives the time from the start of the BS to the detection of the SC as a message signal, and if the SC cannot be detected within the said time, it is sent by some means (for example, by making an alarm horn sound with a different sound than the normal ring tone). Warning. Item 7
, 9 arrange and output the contents of the received message according to a predetermined format (see Tables 5 and 6). Item 8 processes the TS in FIG. 4 [v] as month/day information. Note that TS usually represents time information, and the code structure in each case is shown in Table 2. Next, the pattern in Figure 4 [[ is Figure 5 A (])
It corresponds to signal E in the signal (,) and is used as an end signal.

Now, the decoder 40 in FIGS. 1 and 3 is.

As shown in FIG. 6, the SC detection circuit inputs the received signal into the shift register 500 in series with a clock, thereby determining whether or not the read 31 bits have a predetermined desired pattern. That is, if it is a desired pattern, a match signal is output from the AND GO (AND GO) 540. Further, as shown in FIG. 7, the ID detection circuit receives an input, collates it bit by bit, and inputs the matching output to a counter 600. As a result, the own machine has been called by the detection node output when the number of matching inputs reaches a preset value.

Next, the buffer 70 is provided with a circuit configuration using a transistor and a register, for example, as shown in FIG. The message processing section 60 in FIG. 2 includes an l-chip CPU (message decoder) 100. Random access memory (RAM)
) 300 and an LCD driver 200. The RAM 300 can protect data even when the battery is replaced by a backup circuit composed of a diode 61 and a large-capacity capacitor 63. 1 in the message processing section 6o in FIGS. 1 and 3.
The configuration of the chip CPU 100 is shown in FIGS. 9 and 11, respectively. Further, the decoder 8 in FIG. 3 is provided by the 1-chip CPU shown in FIG. 10, and the functions of each part o7 are as follows. 102-106, 119-121
is an input port, 101, 110 to 118, 122 are output ports), and 107 is an interrupt port.

108 is a serial interface, 120 is a data bus, 130 is a program counter that indicates the contents of an address, 1
40 stores the sequence of instructions to be executed; 76
A program memory for reading out the contents of the address specified by the 0-gram counter 130.

160 is an instruction decoder that decodes information from the f-program memory 140 and supplies control signals corresponding to the instructions to each section; 15° is an ALU (ALU) that performs various operations such as arithmetic operations and logical operations;
tic and Logic Unit), 180
The RAM is used to store various data and save program counts and program status during subroutines and interrupts. Accumulator),
190 is a system clock generation circuit that determines the execution instruction cycle time.

Next, the LCD driver 200 is given in the block configuration shown in FIG.
270 is a command decoder that receives and decodes instructions input through the serial interface 295 and controls each unit according to the content of the instruction; 290 is a 5×7 decoder corresponding to the input data; 28o is a data pointer 250 that specifies an address for writing data from the serial interface 295 or reading data to the real interface 295;
22o is a data memory that stores the output of the character generation circuit 290 or display data from the serial interface 295; 22o is a row driver that controls the rows of the LCD;
10 is a column driver that controls the columns of LCD, 23o is L
LCD voltage controller for controlling voltage to CD, 2
4° is an LCD timing controller that controls the driving timing of the LCD, and 260 is a system clock controller.

Further, the RAM 300 is provided in the professional configuration shown in FIG.
20 is address color/re, 33o is address counter 3
20 is an X-Y decoder for specifying the address of the memory array 340 and writing or reading data into the memory; 340 is a memory array; and 350 is a control circuit.

FIG. 14 shows an example of the configuration of the switching circuit 1.

FIG. 15 shows the data structure of the output signal (g) to the external terminal 5, with 11 pits per character (#). Figure 16 is.

This is an example of a level shift 3 circuit. FIG. 17 is an example of the key arrangement of the data input section.

The operation of the receiver in each case will be explained below.

a) When the desired signal is received after the power is turned on.
As shown in 1), among the receivers in the BS state, when the receiver whose ID corresponds to A1 detects SC after receiving P, it decodes the subsequent signal T1. At this time, since the message data M1 follows, ZO is logic "1", and the BS is released (at least until the next SC, usually further up to A2.I2) for the period represented by the BCD code of Z2 to Z5.
OFF). Furthermore, when decoding I1, 'MC8''
When "1000111" is received as i4 turn, M
The message data of 1 is decoded with the code corresponding to 21, and stored in the RAM 300 and displayed on the LCD 90 via the LCD driver 200. The transmission means 8o is driven through the buffer 70 to notify the owner of the device that he has been called.

Also, calibrate the built-in calendar using the month and day information from I1's °'TS"A? turn.

And the next SC, ID, I2. Detects and decodes I2. At this time, SC is detected, but since the ID signal is A2, it is not detected, so the detection signal DT3 is not output. Therefore, z2 to z5 of I2 and I2(7)MC8””TS
Look at only 7, and after detecting the signal of I2, Z2
~Turn on the BS for the period indicated by Z5 (usually until the next SC), calibrate the built-in clock at the time corresponding to the second turn of "TS" when "MC8" is other than 1000111, and save the reception memory. Adds the reception time to the message.

In this way, when the time for the second SC comes, the BS is turned off again.
becomes. This period is set as the period up to TS because the ID is different from A3 and the built-in clock has already been calibrated. Thereafter, such operations are repeated, and when the end signal E indicating the end of data is detected, the normal BS operation is resumed.

The receiver whose ID corresponds to A3 still detects SC after receiving P, but since the ID does not match at AI, it detects 22 to Z5 of Tl and "T S of T1.
”・Look only at Gutaan. And.

After detecting the signal of I1, turn on BS for the period indicated by 22 to Z5.
At the same time, the built-in calendar is calibrated to the month and day that correspond to the "TS" pattern. In this way, when the time for the next SC comes, the BS will be turned off again for the period up to 2nd, and the SC will be detected but the ID will not be detected, so only z2 to z5 of I2 and °'MC8'" T S " turn of I2 will be detected. I see. Then, after I2 is detected, BS is turned on for a period of 22 to z5.
At the same time, when "MC8" is other than 1000111, the built-in clock is calibrated at the time corresponding to "TS"i+turn. Of course “MC8” pattern dE1000111
In this case, calibrate the built-in calendar using the month and day information that corresponds to the "TS" pattern. In this way, when the time for the first SC comes, the BS is turned off again.6. This is a sc detection operation. Then, when SC,ID is detected, z in I3
While the B S OFF state continues for the period 2 to z5,
"MC3") If the fourth turn is 1000011, the time corresponding to M3 decoded with the code corresponding to Zl is stored. When the built-in clock reaches the predetermined time, the decoder 40 drives the transmission means 80 via the buffer 70, and displays a setting alarm on the LCD 90 (
FIG. 18 is an example). Also, °'TS of I3
Calibrate the built-in clock again using the time information corresponding to '.

Thereafter, when there is no ID corresponding to A3 and the end signal E is received, normal BS operation is resumed.

By the way, in this embodiment, unless the end signal E is received,
, regardless of whether the SC is received or not, the signal T is checked, and if this signal cannot be received correctly, the BS is forcibly turned off for a predetermined period of time (approximately 1 minute in this embodiment).
FF, shifts to receiving the SC signal, and if it is not detected, returns to normal BS operation.Furthermore, if SC is not detected two or more times in a row, it is determined that an electric field is defective and returns to normal BS operation. This aims to make effective use of the information and improve the reliability of reception.

b) When the power is turned on when a desired signal arrives In FIG.
Then, the desired SC signal is detected. When the SC signal is detected in this way.

Although the ID is detected, it is not received, so after the detection of I2, the built-in calendar or clock is calibrated with the 'TS' information according to the 'MC8' pattern, and the
The operation is repeated in which the BS is turned on for a period of , and the BS is turned off again at the 9th SC. In this way, AN
When the ID corresponding to is received, the BS is turned off for the period from 22 to z5 of TN.Tonari, IN(7)MC8'/#
If the turn is 1000101, the data MN is decoded with the code corresponding to 21 of TN and stored. As a result.

If the SC is not detected before returning to BS operation and checking the elapse of time corresponding to the received data on the built-in clock, a warning alarm will be issued to alert you that you are not in a good service area. (When detected, the timer stops and restarts when returning to the BS.) Then, the BS is forcibly turned off for a predetermined period of time (approximately 1 minute in this example), and SC detection is performed. If SC is not detected within the predetermined period, the operation of returning to the BS operation will be repeated.

C) Registration/reading by manual input of fixed form information Select the desired key from the mode SW of the data input section 2 (However, if you select the "CAL" or "'TIME" key, the LC
D90 operates as a computer function or a clock function in conjunction with the CPU). If you press the "Place" key here,
An interrupt is applied from the terminal of the interrupt port 107 in FIG. 9, and at the same time, a key or a turn corresponding to the "place" key is input from the input port 102.

As a result, the CPU recognizes that the device is set to the "position" mode, and inputs data from the capo 103.

For example, “DATAIN”, “AoKr”, “p
AT, uN”, “NEC”.

"DATAIN", "03-262-5174",
“DATAIN”, “KUDO”, “DATA”
"IN", "5ONY', . . . are input. After confirming the result entered manually, it is read out according to the predetermined format (see Table 5), and first °'D
When you press the ATAOUT# key, "AOKI" is displayed on the LCD, and when you press the °'→" key, "NEC" is displayed. When you press the °'→" key, "03-262-5174" is displayed, and then "1" is displayed. →"Press the key to 'KUDO'.

Next, press the "→" key to confirm °'ENDO, and press the "'→" key to confirm "5ONY."

Similarly, if you press the "MEMO" key, the interrupt port in Figure 9 will appear.
At the same time, an interrupt is generated from the terminal 107, and a turn "OO10011" corresponding to the °'MEMO" key is input from the input port 102. As a result, the CPU determines that the device is set to the "MEMO" mode. , the following data input from the input port 103 [”
DATA IN”,”FEB,10.19845CHE
DULE', "DATAIN", "9:00""DAT
A IN", '"MEETING(NEW PRO
DUCT) AT5-1”, “DATA IN”, '10
:30",...] to read "DATA OU"
When you press the T” key, °゛FEB, 10.1984SCHEDULEnFEB, 1 will be displayed on the LCD 90 as shown in Table 6.
0.1984SCHEDULEnThe display changes to "9:00", and when you press the ^→" key, the display changes to PAYA ET ING.
(NEW PRODUCT) AT S-1" and then press the "P↓" key to change to "(NTTMRKUDO)", allowing you to check the necessary information at any time with simple operations instead of using a memo pad.

Furthermore, this receiver has a built-in calendar and a built-in clock, so FEB, 10"'9:00".

At the date and time of ``10:30'', etc., the receiver's transmission device (for example, an alarm horn) is activated to alert the user, and a display corresponding to the sounding time is displayed on the LCD 90. For example, If it is 18:00, “GINZA (M
ORE)” will be displayed on the LCD.

d) Registration of fixed form information by wireless The operation of the receiver will be explained using FIGS. 1, 9, 12, and 13.

A radio section 20 of a receiver performing BS operation with the switching circuit 1. When voltage is applied to the waveform shaping circuit 30,
When a preamble signal P is received.

B S is kept OFF for a period sufficient to detect a subsequent predetermined synchronization signal SC. And during this time SC
When detected, interrupt port 1 is detected/Grus DT2
07, the CPU 100 is activated, and the decoder 40 shifts to an ID detection operation. That is, starting from the detection of the SC, the data in the P-ROM 50 in which the ID number of the own machine is written is compared bit by bit with the received data (Fig. 7), and when a match is confirmed, the The detection pulse DT3 is input to one chip CPU (00) through the input port 121, and a clock CL corresponding to the transmission speed is supplied from the input port 105.

At this time, DT3 is activated after a predetermined period of time (time until DT3 is detected) from the interrupt activation by DT2.
If this is input, it is determined that the ID has been detected, and if not, it is determined that the IDs match, and preparations are made to receive the subsequent signal. As a result, the 1-chip CPU 100 reads the message signal from the input port 106 using the clock CL, translates the predetermined contents of the program memory 140 using the instruction decoder 160, and processes it in accordance with each instruction. That is, the read signal is transferred to the RAM 18 via the data bus 120 and the ACC 170.
Written to 0. Thus, each time the 31 bits forming the BCH (31, 21) code are input, the ALU 150
performs calculations and decodes the received signal.

The 1-chip CPU 100 reads the first decoded BCH (
31, 21) Decode the 20 information bits of the code according to Fig. 4 [■], and from then on output port 1
12 to control the BS operation of the receiver. At this time,
If the 20-bit information is the following Noreen, rllo
Lo 0000000000100000'' call is accompanied by a message, the message data is 7 bits long, and indicates that the BS must be cleared for at least 20 words (here, 1 word is 31 bits).

Then, it waits for the input of the secondary 31 bits and decodes the signal (2). In this way, the 20-bit information area is analyzed according to Tables 1 and 2 in FIG. 4 [■]. That is, if the information bit is ・nitar/ as follows, then 11100011
00101000100000 J Indicates that the subsequent message data will be processed in the telephone directory mode, and indicates that the data transmission time is AMlo: 20 minutes.

Subsequent messages are processed in accordance with the control content decoded in this manner. Therefore, 3
Information area where each bit is decoded (20 bits,
data) is decoded in 7-bit units and sequentially stored in external RAM.
3 Q Stored in Q.

That is, by setting the chip select C81 to the logic "On level," the RAM 300 is placed in the operation mode, and the RAM
300, the corresponding address information is sent via the serial interface 108 to the signal line SO.
Transfer with . At this time, the 1-chip CPU 100 sends the system clock signal to the RAM 300 using SCK, and at the same time sets the signal line 6 to a logic level 1'' to indicate that it is an address.
level. At this time, in Figure 13, R
AM 300 receives each input control signal (C8, A/D,
R/v).

The signal input from the signal line SO is determined to be an address signal, and the address to be written in the memory array 340 is designated via the address counter 320 and the X-Y decoder 330.

Next, the 1-chip CPU 100 sends the message data to be written to the signal line SO of the serial interface 108.
At the same time, the signal line V is set to logic "0" level to indicate that the data to be sent is message data, and the signal line R/W is set to logic "0" level to instruct writing.

As a result, the RAM 300 in FIG. 13 sends the data input via the signal line SO as message data via the XY decoder 330 to the memory array 340 in response to each input control signal. Write to the specified address.

When message data is sequentially decoded in the above process, in BCH (31, 21) units, SC
Alternatively, when an end code is detected or two consecutive words cannot be received, the 1-chip CPU 100 determines that the message data has ended, and connects the signal line M from the output capo 110.
The decoder 40 notifies the end of the message via the signal line A via the output port 111.
C drives the sound generation circuit of the decoder 40. The resulting signal (d).

An alarm horn 80 sounds via the buffer 70.

Here, in the case of SC detection, the 1-chip CPU 100 repeats the same operation as described above, but when receiving the end code or
If consecutive words are not received, the receiver returns to BS operation.

As described above, a code corresponding to the desired content is input to the receiver as a normal message.

Next, in order to read the data received and stored in this way, by pressing the read switch S1, the 1 chip CPV 100 supplies the first address information of the corresponding message data from the signal line SO to the RAM 300, and The enable signal line C81 is at logic "0" level, the chip select signal line i (this is the LCD driver 20
This is a signal line for selecting 0. ) and signal line A/I
) is set to logic "1" level. Next, connect the signal line layer 6 to logic
0" level and the signal line R/W is set to logic "1" level. As a result, the data corresponding to the above-mentioned first address is sent in byte units to the memory array via the X-Y decoder 330. 340, and the data is supplied to the 1-chip CPU 100 via the serial interface 310 and the signal line SI.In this way, the data is also read from the RAM 300 and is supplied to the 1-chip CPU 100 via the serial interface 310 and the signal line SI.
When supplied to PU 100.

Character conversion is performed from the signal line SO by setting the signal line i and signal lines c and f to the logic ``1'' level, and by setting the chip select signal line C82 to the logic ``0'' level to select the LCD driver 200. The instruction and storage address information are supplied to the LCD driver 200. Next, the 1-chip CPU 100.

RAM by setting the signal line to logic ``0#'' level.
3 Q The data read from Q is supplied to the LCD driver 200 via the signal line SO.

As a result, in the LCD driver 200 shown in FIG.
The serial interface circuit 295 converts the information into 7 real-to-gray parallel signals, and the signal line C/I) becomes the logic "1".
The level information is decoded by a command decoder 270, and the command decoder 270 generates an internal control signal.

Here, if the command is a write command and a character conversion command.

Data pointer 280 to set write address
is accessed and the signal line C/D goes to the logic "0" level, the data input via the serial interface 295 is converted into a 5x7 dot matrix pattern by the character generation circuit 290, and is stored in the data memory. 250 and displayed on the LCD 90 as signal C via column driver 210 and row driver 220 under the control of LCD timing controller 240.

e) Registration/Change of Common ID The operation of the receiver will be explained using FIGS. 3, 10, and 11.

FIG. 3 shows the decoder 40. This is a partially modified configuration of the message data 60 (Figure 11 shows an example of the configuration of the CPU 100), especially the R for common ID.
Decoder 8 (1 chip f in this example) serves as an AM and decoder.
The system uses a CPU (the configuration of which is shown in FIG. 10).

Now, the radio section 20 of the receiver that performs BS operation in the switching circuit 1. When a voltage is applied to the waveform shaping circuit 30 and the 7'lJ ampoule signal P is received, the BS operation is stopped for a period sufficient to detect a subsequent predetermined synchronization signal SC.

If SC is detected during this period, the detected value is J? 1 chip CPU via interrupt port 107 on Ruth DT2.
100 and decoder 8 and decoder 40
starts from the detection of the SC and compares bit by bit with the data in the P-ROM 50 in which the individual selective call number of the own machine is written.

If the received data matches the individual calling number of the own machine in the P-ROM 50, the detection signal DT3 is inputted from the input port 121 in FIG. As a result, the CPU activated by the SC detection pulse DT2 determines that the input is from the input hoard 121 instead of the input hoard 119 at the time when the ID should be detected, and recognizes that the detected ID is an individual selection call number.

Prepare to receive the message signal that will be sent subsequently.

That is, in the one-chip CPU 100, the signal following the ID is read from the input port 106 using the clock CL, and the signal is read from the data bus 120. Write to RAM 180 via accumulator ACC 170. Thus BCH (31,
21) Every time the 31-bit data forming the code is input, the ALU 150 performs an operation and decodes the received signal. Of the 31 decoded bits, 20 information bits are decoded according to FIG.

At this time, if the 20 bits of information are the following turn, rllolo 00000000
00110010J indicates that the call has message information consisting of a 7-bit code and indicates that it is necessary to cancel the 32-word BS operation. That is, the 1-chip CPU 100 sets and starts a 32-word timer.

Then, it waits for the secondary 31-bit input and performs signal decoding. The 20-bit information area thus obtained is analyzed according to Tables 1 and 2 in FIG. 4 [V] 1. That is, if the information bit has the following pattern, rl 1
0000011001000110110j, which is registered as a common ID in the subsequent message data, means that the current time is 2:36 PM.

Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the subsequent message data is decoded every 31 bits, of which 20 bits are decoded into 7-bit units. Here, the 20-bit information technology J of the received message
If JA's turn is as follows, use Table 2 and 6.

-15-J-10-J-N- J-Y-"-(" SONY brand, ID roiioi...0.1101
1 J is registered, but 1 Tetsuzo CPU 100 is RAM
A label of 5ONY is attached to an empty number in the common ID area of 300, and the corresponding number and ID/# turn of the ID area are transferred to the decoder 8.

That is, the chip select C84 is set to logic "0" level, and the common ID area number (for example, 0110=6) and ID pattern [01101...0LIOIIJ are output from the serial output SO along with the system clock SCK.

At this time, the chip enable CE of the decoder 8 becomes logic "0", so the decoder 8 prepares for reception and sends the data input along with the subsequent 7 stem clocks to the serial manual SI.
From/Real Interface 108. data bus 120
Via.

Register it as the 6th ID in RAM 18'O.

Also, if the pattern of information bits of the received signal I is the following two turns, rlloooo 0100101
000110000j, the common ID that is changed in the subsequent message data is missing, and the time at the time of sending is AMII: 3
It means 0. And 2 of the received messeno
If the pattern 7 in the 0-bit information area is as follows, then the 11th
1 chip CPU 100 in the figure is -1-T-+/℃-1-J--1J□DEL1-1-chip N+++7S+
+E + Tomoe S” Tomoe 0110 001011.10101001000000-1sho-
J RAM 3 Q Q common ID area label TDK
Search for the area corresponding to , change from TDK to NEC, set chip select C54 to logic "O" level, and connect common I from 7 real output SO with /stem clock SCK.
D area number and ID/? Turn “011010...0
111" is output. As a result, the input data is written in the area corresponding to the ID number in the RAM of the decoder 8.

In this way, when the detection of SC is confirmed with the common ID registered in the decoder 8, the decoder 8 receives the input signal CL corresponding to the transmission speed and J
Since data D following the SC is supplied from the input port 105, the data D following the SC is read from the input port 106, the predetermined contents of the program memory 140 are translated by the instruction decoder 160, and processed in accordance with each instruction.

That is, the above-mentioned read data is compared bit by bit by the ALU 150 via the data bus 120 with the common ID (if there is more than one) registered in advance in the RAM 180.

If a match with the common ID is confirmed, the data detection information DI is sent to the output port 113.

One chip in the message processing section 60 is a CPU 100 (first
1), and information DE indicating whether the detected ID is the number in the common ID area is output from the output port 114 to the 1-chip CPU 100.

The 1-chip CPU 100 recognizes that a common ID has been received by a signal from the input port 119 during a certain period of time used for ID detection after interrupt activation by the detection pulse DT2 of the SC, and inputs the subsequent common ID area information to the input port. 12
Read from 0.

In order to store the message data received as a result in the RAM 300, the chip select C81 is set to the logic "O" level, and the address information corresponding to the data from the input port 120 is transferred from the signal line SO via the serial interface 108. . At this time, 1ch, 7'CPU1
00 is sent by the system clock SCK, and at the same time, the signal line A/I) is set to logic 1" to specify that it is an address.
level.

When the address setting of the RAM 300 is completed in this manner, the A/D is set to logic "0" level and the received message data is written into the designated address area of the RAM 300 from the signal line SO.

In addition, when outputting the received message data to the outside, the chip select C83 is set to logic "0", and the configuration of one character is set to the output port 122 in the format shown in FIG.
The signal is then output to the level shift circuit 3. Here, if a signal processing unit that can be connected to the external terminal 5 of the receiver is used,
It is possible to apply desired processing to data received via wireless.

Here, the receiver has two individual selective calling numbers and a common I as ID.
D, it is conceivable that each of the RAMs 3 and 3 has separate messeno storage areas. Then, if you want to change the distribution of that area,
It can be arbitrarily set using C8-4' turn and message data.

Margin below (Table 4) (Table 5) FEB, 10.1984 5CHEDULE
(Table 6) [Effects of the Invention] As explained above, according to the present invention, at least the frame synchronization signal 2 selection call signal, the control signal, and the message signal are configured in this order. Means for decoding the content of the subsequent message in a predetermined format corresponding to the predetermined code and registering it in the receiver as a common address or changing or deleting the already registered common ID. A wireless selective calling receiver capable of receiving message information provided therein can be provided.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a wireless selective calling receiver with display;
FIG. 2 is a block diagram of the message data processing unit 60, FIG. 3 is a second block diagram of the wireless selective calling receiver with display, and FIG. 4 is a signal diagram, where [I] is a prefix. Signal pattern, [■] is synchronization signal / pattern, [■] is address signal and message signal configuration pattern, [■]
] is the configuration of the first control signal) e turn, [v] is the configuration of the second control signal, and [■] is the end signal and turn, respectively. 1) and A (If) are both time charts for normal operation. FIG. 5B is a diagram showing a time chart of the operation when the power is turned on after the preamble signal, and FIG. 6 is a block diagram showing the synchronization signal and end signal detection circuit.
FIG. 7 is a block diagram showing the address detection circuit, FIG. 8 is a circuit configuration diagram of the buffer 70, and FIG. 9 is a 1-chip CPU.
100 professional configuration diagram, Figure 10 shows 1 chip, CPU
8, FIG. 11 is a block diagram of the one-chip CPU 100 in the message processing unit 60 of FIG. 3, FIG. 12 is a block diagram of the LCD driver 200, and FIG. 13 is a block diagram of the external RAM 300. FIG. 14 is a block diagram of the switching circuit 1. FIG. 15 is a diagram showing the output data format from the data input section 2, FIG. 16 is a configuration diagram of the level shift circuit 3, FIG. 17 is a diagram showing the key arrangement of the data input section 2, and FIG. 18 is a setting diagram. FIG. 19 is a diagram showing an example of a display indicating a warning, and is a diagram showing, as an example of battery saving, that the battery is turned on in the time slot (G7) of the group to which the own aircraft belongs. 8 is a decoder, 10 is an antenna, 20 is a radio section, 30 is a waveform shaping circuit, and 40 is a decoder. 50 is a P-ROM, and 60 is a message data processing section. 61 and 62 are diodes, 63 and 64 are capacitors, 70 is a buffer, 80 is an alarm horn (transmission means), 90 is an LCD, and 100 is a chip. CPU (message decoder), 101/110-
118 is an output port, 102-106 and 119 are input ports), 10'7 is an interrupt port, 108 is a serial interface, and 120 is a data bus. 130 is a program counter, 140 is a program memory, 150 is an ALU, 160 is an instruction decoder, 170 is an ACC 2180 is a RAM. 190 is a system clock generation circuit, 200 is an LCD driver, 210 is a column driver, 22° is a row driver, 230 is an LCD voltage control controller, 240 is an L
CD timing controller. 250 is a data memory, and 260 is a system clock. controller, 270id command coater. 280 is a data pointer, 29o is a character generation circuit, and 295 is a serial interface. 300 is an external RAM, 310 is a serial interface, 320 is an address counter, 33o is an X-Y decoder, 340 is a memory array, 35° is a control circuit,
500 is a shift reno star, 510-530 are inverters, and 540 is an AND gate. 600 is Karan 1, 610 is EXNOR+”-to, 7
10.720 is resistance, 730 is NPN) Lannostar,
74° is a PNP) transistor, 800 is an alarm horn. 1a is PNP I-lannosta, lb and 3c are NP
Each of the N transistors is exposed. Fig. 2 Fig. 3 Fig. 4 Fig. 5 A(I,) (Jshi'koro-) - Ichikanriki-71 Fig. 12 Fig. 13 Hemorrhoids Fig. 14

Claims (1)

[Claims] 1. Individual selective calling that starts a detection operation in response to a detection pulse of a synchronizing signal when receiving a calling signal consisting of at least a synchronizing signal, a selective calling signal, a control signal, and a message signal in this order. a detection means, a common call detection means, which responds to the detection pulse of the individual call detection means, decodes the message symbol in accordance with a predetermined pattern of the control signal, and detects a selective call number of the common call means; A wireless selective call receiver capable of receiving messages compatible with multiple addresses, characterized by having means for changing the contents of a storage area. 2. The radio selective call reception capable of multi-address message reception as set forth in claim 1, characterized in that the common call detection means and its selective call number storage area are realized by a single-chip CPU. Machine.