JPS6194366A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS6194366A JPS6194366A JP59215134A JP21513484A JPS6194366A JP S6194366 A JPS6194366 A JP S6194366A JP 59215134 A JP59215134 A JP 59215134A JP 21513484 A JP21513484 A JP 21513484A JP S6194366 A JPS6194366 A JP S6194366A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- thin film
- semiconductor thin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は非晶質シリコン等の半導体薄膜を用いた薄膜ト
ランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film transistor using a semiconductor thin film such as amorphous silicon.
近年、薄膜形成技術の進歩により良質の非晶質半導体薄
膜が得られるようになり、薄膜トランジスタが注目を集
めている。この薄膜トランジスタは、例えば透明基板上
にマトリクス伏に多数形成されてアクティブマトリクス
タイプの液晶表示装置に利用されている。In recent years, advances in thin film formation technology have made it possible to obtain high quality amorphous semiconductor thin films, and thin film transistors have been attracting attention. For example, a large number of thin film transistors are formed in a matrix on a transparent substrate and used in an active matrix type liquid crystal display device.
第4図は従来の薄膜トランジスタの一例を示す図で、ガ
ラス基板(1)上にソース電極(2)及びドレイン電極
(3)が形成され、この2つの電極(2) 、 (3)
上には更に不純物ドープ非晶質シリコン膜(4)が形成
されている。そして2つの電極(2) 、 (3)を覆
うようにアンドープ非晶質シリコン膜(5)が形成され
ている。FIG. 4 is a diagram showing an example of a conventional thin film transistor, in which a source electrode (2) and a drain electrode (3) are formed on a glass substrate (1), and these two electrodes (2), (3)
An impurity-doped amorphous silicon film (4) is further formed thereon. An undoped amorphous silicon film (5) is formed to cover the two electrodes (2) and (3).
ここで不純物ドープ非晶質シリコン膜(4)は、このア
ンドープ非晶質シリコン膜(5)と2つの電極(2)。Here, the impurity-doped amorphous silicon film (4) is connected to this undoped amorphous silicon film (5) and the two electrodes (2).
(3)とのコンタクトを良好にする働きをもっている。(3) It has the function of improving contact with.
そして酸化シリコンや窒化シリコン等の絶縁膜(6)が
、アンドープ非晶質シリコン(5)を覆うように形成さ
れ、更に絶縁膜(6)上にはゲート−1極(7)が形成
されている。Then, an insulating film (6) such as silicon oxide or silicon nitride is formed to cover the undoped amorphous silicon (5), and a gate-1 pole (7) is further formed on the insulating film (6). There is.
〔背景技術の問題点コ
しかしこの薄膜トランジスタにおいては、形成されたア
ンドープ非晶質シリコン膜(5)の膜質力、ソース電極
(2)及びドレイン電極(3)の段差部上とこれ以外の
部分では異なる場合がある。これにより薄膜トランジス
タの特性が悪かったり、アンドープ非晶質シリコン膜(
5)の選択エツチング時にエツチングの不均一を生じて
所定の形状を得ることが困難になったりすることがある
。[Problems in the Background Art] However, in this thin film transistor, the film quality of the formed undoped amorphous silicon film (5) is different between the step portions of the source electrode (2) and the drain electrode (3) and the other portions. It may be different. This may result in poor characteristics of thin film transistors or undoped amorphous silicon films (
During selective etching (5), non-uniform etching may occur, making it difficult to obtain a predetermined shape.
本発明はこのような従来の欠点を解決するためになされ
たもので、形成する半導体薄膜の膜質を均一にすること
の可能な薄膜トランジスタの提供を目的とする。The present invention has been made to solve these conventional drawbacks, and an object of the present invention is to provide a thin film transistor in which the quality of the formed semiconductor thin film can be made uniform.
即ち本発明は、複数個の凹部を設けた絶縁性基板と、凹
部に埋設したソース電極及びドレイン電極と、ソース電
極とドレイン電極にわたり形成された半導体薄膜と、半
導体薄膜上に形成された絶縁膜と、絶縁膜上く形成され
たゲート電極とを備えたことを特徴とする薄膜トランジ
スタであり、半導体薄膜の下地となる表面の段差が従来
より低減されている。That is, the present invention provides an insulating substrate having a plurality of recesses, a source electrode and a drain electrode buried in the recesses, a semiconductor thin film formed over the source electrode and the drain electrode, and an insulating film formed on the semiconductor thin film. This is a thin film transistor characterized by comprising a gate electrode formed on an insulating film and a gate electrode formed on an insulating film, and the level difference on the surface underlying the semiconductor thin film is reduced compared to the conventional one.
以下本発明の詳細を図面を参照して説明する。 The details of the present invention will be explained below with reference to the drawings.
第1図は本発明の一実施例を示す図で、絶縁性基板a1
例えばガラス基板に設けられた複数個の凹部(11)に
、ソース電極(12及びドレイン電極αy例えばITO
が埋設されている。更にこの2つの電極(1シ。FIG. 1 is a diagram showing an embodiment of the present invention, in which an insulating substrate a1
For example, in a plurality of recesses (11) provided in a glass substrate, source electrodes (12 and drain electrodes αy, for example, ITO
is buried. Furthermore, these two electrodes (1 shi.
(13上にはそれぞれ、リン添加の不純物ドープ非晶質
シリコン膜(14)が形成されていて、不純物ドープ非
晶質シリコン膜Iの表面と絶縁性基板部の表面とは段差
がなく平滑になっている。そして絶縁性基板αQ上には
、ソース電極f13とドレイン電極03にわたり半導体
薄膜α9例えばアンドープ非晶質シリコン膜が形成され
ている。ここで不純物ドープ非晶質シリコンN(14)
は、この半導体薄膜(1つと2つの電極([2、(13
とのコンタクトを良好にする働きを持っている。そして
半導体薄膜a9を覆うよって絶縁膜[9例えば酸化シリ
コンまたは窒化シリコンが形成され、更に絶縁膜C10
上にはゲートTX極αη例えばアルミニウムが形成され
ている。(A phosphorus-doped impurity-doped amorphous silicon film (14) is formed on each of the 13, and the surface of the impurity-doped amorphous silicon film I and the surface of the insulating substrate part are smooth without any step. A semiconductor thin film α9, for example, an undoped amorphous silicon film, is formed on the insulating substrate αQ over the source electrode f13 and the drain electrode 03. Here, an impurity-doped amorphous silicon film N(14) is formed.
is this semiconductor thin film (one and two electrodes ([2, (13
It has the function of improving contact with people. Then, an insulating film [9, for example, silicon oxide or silicon nitride] is formed to cover the semiconductor thin film a9, and an insulating film C10 is formed to cover the semiconductor thin film a9.
A gate TX pole αη, for example aluminum, is formed thereon.
次にこの実施例の製造方法について述べる。第2図はこ
の一例を示す図である。まず第2図(alに示すように
、絶縁性基板(1Gにレジストパターン(IQを形成し
た後、これをマスクとして絶縁性基板(10)の表面を
200OAだけエツチングし凹部(lDt−形成する。Next, the manufacturing method of this example will be described. FIG. 2 is a diagram showing an example of this. First, as shown in FIG. 2 (al), after forming a resist pattern (IQ) on an insulating substrate (1G), using this as a mask, the surface of the insulating substrate (10) is etched by 200 OA to form a recess (1Dt-).
次に第2図(blに示すように、レジストノくターン賭
を残したまま絶縁性基板部の全面に、ソース電極αり及
びドレイン電極(13の材料となる膜(11と不純物ド
ープ非晶質シリコン膜α4とをこの順にそれぞれ150
0λ、500λの厚さに形成する。そして第2図(cl
に示すように、レジストパターン舖を除去することによ
り絶縁性基板部上の2つの膜<141 。Next, as shown in FIG. 2 (bl), a film (11 and an impurity-doped amorphous film) which is the material of the source electrode and drain electrode (13) is coated on the entire surface of the insulating substrate part with the resist notch remaining. silicon film α4 and 150 μm each in this order.
It is formed to a thickness of 0λ and 500λ. And Figure 2 (cl.
As shown in FIG. 1, two films on the insulating substrate part are removed by removing the resist pattern.
(1’lをり7トオ7し、凹部(11)にソース電極住
z1 ドレイン電極03及び不純物ドープ非晶質、シ
リコン膜α滲を埋設する。次に第2図(d)に示すよう
に、半導体薄膜(Isを3000λの膜厚で堆積した後
所定の)くターンニエッチングする。そして第2図(e
)K示スヨうに、絶縁膜茜とゲート電極αηの材料とな
る膜とをこの順にそれぞれ4000λ、1μmの厚さに
堆積した後、上の方の膜を所定のパターンにエツチング
してゲート電極(1′l)を形成する。こうして所望の
薄膜トランジスタが得られる。(Remove 1'l and fill in the recess (11) with the source electrode, drain electrode 03, and impurity-doped amorphous silicon film.Next, as shown in FIG. 2(d), , a semiconductor thin film (Is is deposited to a thickness of 3000λ and then etched in a predetermined number of turns).
) As shown in the diagram, after depositing the insulating film and the film that will become the material for the gate electrode αη in this order to a thickness of 4000λ and 1 μm, the upper film is etched into a predetermined pattern to form the gate electrode ( 1'l) is formed. In this way, a desired thin film transistor is obtained.
第3図はこの実施例の製造方法の別の例を示す図である
。まず第3図(a)に示すように、絶縁性基板Q〔の表
面を4 ’000λだけエツチングし凹部αυを形成す
る。次に第3図(bl−に示すように、ソース電極U及
びドレイン電極α3の材料となる膜住9と不純物ドープ
非晶質シリコン膜Iとをこの順にそれぞれ1500χ、
3500λの厚さに形成した後、平滑材料(イ)例えば
ポリイミドまたはフォトレジストを塗布して平滑化し、
凹部(Ll)上の平滑材料の膜厚を1,5μm程度にす
る。そして第3図(C)に示すように、平滑計料翰と膜
(14,α1と絶縁性基板α■のエツチング速度がすべ
て等しくなるように設定した条件でのILIB法等によ
り、これらを全部で1.7μm程度エツチングする。次
に第3図(d) K示すように、半導体薄膜(L5を3
000λの膜厚で堆積した後所定のパターンにエツチン
グする。そして第3図(e)に示すように、絶縁膜−と
ゲート電極αηの材料となる膜とをこの順にそれぞれ4
0001.1μmの厚さに堆積した後、上の方の膜を所
定のパターンにエツチングしてゲート電極(I7)を形
成する。こうして所望の薄膜トランジスタが得られる。FIG. 3 is a diagram showing another example of the manufacturing method of this embodiment. First, as shown in FIG. 3(a), the surface of the insulating substrate Q is etched by 4'000λ to form a recess αυ. Next, as shown in FIG. 3 (bl-), the film layer 9 and the impurity-doped amorphous silicon film I, which are the materials of the source electrode U and the drain electrode α3, are each coated in this order with a thickness of 1500χ.
After forming it to a thickness of 3500λ, smoothing it by applying a smoothing material (a) such as polyimide or photoresist,
The thickness of the smooth material on the recess (Ll) is about 1.5 μm. Then, as shown in Fig. 3 (C), all of them were etched by the ILIB method under conditions set so that the etching rates of the smoothing plate, the film (14, α1, and the insulating substrate α■) were all the same. Next, as shown in Fig. 3(d), the semiconductor thin film (L5 is etched by 3
After the film is deposited to a thickness of 000λ, it is etched into a predetermined pattern. Then, as shown in FIG. 3(e), the insulating film and the film that is the material of the gate electrode
After being deposited to a thickness of 0001.1 μm, the upper film is etched into a predetermined pattern to form a gate electrode (I7). In this way, a desired thin film transistor is obtained.
今まで述べたようKこの実施例では、ソース’tN極(
121及びドレイン電極α3を絶縁性基板(IIの凹部
αυに埋設して、絶縁性基板(11の表面に段差がほと
んどない状態で半導体薄膜α9を堆積している。故に半
導体薄膜住9は、場所による膜質の不均一を生じること
がなく、半導体薄膜(lE9の選択エツチング時にエツ
チングの不均一が生じないため、所定の形状を容易に得
ることができる。また薄膜トランジスタの導通部に異質
な膜質が存在しないため、特性の良好な薄膜トランジス
タを得ることができる。As mentioned above, in this embodiment, the source 'tN pole (
121 and the drain electrode α3 are buried in the recess αυ of the insulating substrate (II), and the semiconductor thin film α9 is deposited on the surface of the insulating substrate (II) with almost no steps. Because non-uniformity in film quality does not occur during selective etching of the semiconductor thin film (lE9), a predetermined shape can be easily obtained.Also, there is non-uniform film quality in the conductive part of the thin film transistor. Therefore, a thin film transistor with good characteristics can be obtained.
以上説明したように本発明の薄膜トランジスタは、ソー
ス電極及びドレイン電極を絶縁性基板に設けた凹部に埋
設してなるので、半導体薄膜を形成する際の絶縁性基板
上の段差が従来より少ない。As explained above, in the thin film transistor of the present invention, the source electrode and the drain electrode are embedded in a recess provided in an insulating substrate, so there are fewer steps on the insulating substrate when forming a semiconductor thin film than in the past.
よって半導体薄膜を膜質が均一になるように形成でき、
その特性は良好なものとなる。Therefore, semiconductor thin films can be formed with uniform film quality,
Its characteristics are good.
第1図は本発明の一実施例を示す図、第2図と第3図は
本発明の製造方法の一例を示す図、第4図は従来の薄膜
トランジスタの一例を示す図である。
■・・絶縁性基板 (11)・凹部鰺・ソース電
極 (13ドレイン・シ柵(へ)半導体薄膜
住e・・絶縁膜住η・・・ゲート電極
代理人 弁理士 則 近 憲 佑 (ほか1名)第2図
(a>
ttジノ(C)
<d)(eン
tti rl
第3図
(rL) Lδ〕
tc)td)
(e)
第4図FIG. 1 shows an embodiment of the present invention, FIGS. 2 and 3 show an example of the manufacturing method of the invention, and FIG. 4 shows an example of a conventional thin film transistor. ■・Insulating substrate (11)・Concave part・Source electrode (13 Drain・Semiconductor thin film
Housing e... Insulating film housing η... Gate electrode agent Patent attorney Nori Chika Kensuke (and 1 other person) Figure 2 (a>
tt Jino (C)
<d) (entti rl Fig. 3 (rL) Lδ] tc) td) (e) Fig. 4
Claims (1)
したソース電極及びドレイン電極と、前記ソース電極と
前記ドレイン電極にわたり形成された半導体薄膜と、前
記半導体薄膜上に形成された絶縁膜と、前記絶縁膜上に
形成されたゲート電極とを備えたことを特徴とする薄膜
トランジスタ。an insulating substrate provided with a plurality of recesses, a source electrode and a drain electrode buried in the recesses, a semiconductor thin film formed across the source electrode and the drain electrode, and an insulating film formed on the semiconductor thin film. , and a gate electrode formed on the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215134A JPS6194366A (en) | 1984-10-16 | 1984-10-16 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215134A JPS6194366A (en) | 1984-10-16 | 1984-10-16 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6194366A true JPS6194366A (en) | 1986-05-13 |
Family
ID=16667265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59215134A Pending JPS6194366A (en) | 1984-10-16 | 1984-10-16 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6194366A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62299082A (en) * | 1986-06-18 | 1987-12-26 | Fujitsu Ltd | Thie-film transistor |
| JPH0395937A (en) * | 1989-09-07 | 1991-04-22 | Toshiba Corp | Soi type semiconductor device and manufacture thereof |
| JPH0449625A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Thin-film transistor and its manufacturing method |
| JP2006332660A (en) * | 2005-05-27 | 2006-12-07 | Samsung Sdi Co Ltd | ORGANIC THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ORGANIC ELECTROLUMINESCENT DISPLAY |
| JP2011211185A (en) * | 2010-03-08 | 2011-10-20 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing the same |
| CN103000669A (en) * | 2011-09-09 | 2013-03-27 | 中国科学院微电子研究所 | Source-drain buried graphene transistor device and fabrication method on diamond-like substrate |
| CN105609561A (en) * | 2016-01-27 | 2016-05-25 | 无锡盈芯半导体科技有限公司 | Graphene radio frequency transistor and manufacturing method therefor |
| CN110164965A (en) * | 2019-04-22 | 2019-08-23 | 中国科学院微电子研究所 | A kind of semiconductor devices and preparation method |
-
1984
- 1984-10-16 JP JP59215134A patent/JPS6194366A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62299082A (en) * | 1986-06-18 | 1987-12-26 | Fujitsu Ltd | Thie-film transistor |
| JPH0395937A (en) * | 1989-09-07 | 1991-04-22 | Toshiba Corp | Soi type semiconductor device and manufacture thereof |
| JPH0449625A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Thin-film transistor and its manufacturing method |
| JP2006332660A (en) * | 2005-05-27 | 2006-12-07 | Samsung Sdi Co Ltd | ORGANIC THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ORGANIC ELECTROLUMINESCENT DISPLAY |
| JP2011211185A (en) * | 2010-03-08 | 2011-10-20 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing the same |
| US10749033B2 (en) | 2010-03-08 | 2020-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| CN103000669A (en) * | 2011-09-09 | 2013-03-27 | 中国科学院微电子研究所 | Source-drain buried graphene transistor device and fabrication method on diamond-like substrate |
| CN105609561A (en) * | 2016-01-27 | 2016-05-25 | 无锡盈芯半导体科技有限公司 | Graphene radio frequency transistor and manufacturing method therefor |
| CN110164965A (en) * | 2019-04-22 | 2019-08-23 | 中国科学院微电子研究所 | A kind of semiconductor devices and preparation method |
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