JPS6198436A - Input/output control system - Google Patents

Abstract

PURPOSE:To decrease the number of interruptions to a CPU and at the same time to attain the logical copying job of a file at a high speed, by storing the control information in a table. CONSTITUTION:A CPU1 transfers successively the files to be copied to a main memory from a DKU5. A table is produced on the main memory to give the start to an MTU after a proper number of blocks are read out of the DKU5. When the production of said table is through, the VT flag is set at '1' in the control information area of the table. Then the head address of the table is designated and started to an MTC2. The MTC2 receives the head address of the table and extracts data out of the value of the head address to store it in a RAM106. An MTU3 gives a request for data to a control circuit 205 when the MTU3 is ready for reception of data. With reception of said request, a route is formed as a main memory a data register 102 a data buffer 202 the circuit 205 the MTU3. Then the transfer of data is started.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention operates a microprogram stored in a magnetic tape control device according to an input/output control method, a patent, and instructions output from a central processing unit. Input/output control that controls 7-aisle logical copy operations between a magnetic disk device and a magnetic tape device with a streaming function via the main memory.

Regarding the method.

(Prior art) In general, the input/output control method of microprogram control is
It operates in response to commands output from a central processing unit (hereinafter referred to as CPU). These commands include write commands and read commands. Conventionally, when transferring data between an input/output device (hereinafter referred to as I10 device) and a CPU, when the CPU issues a command to the input/output control device, the input/output control device decodes this command and sends a command to the I10 device. It sends necessary commands and controls direct memory access (hereinafter referred to as MA) data transfer to perform data transfer.

When the data transfer is completed, the input/output control device notifies the CPU of the completion of the operation via an interrupt.

Next, a more detailed explanation will be given with reference to the drawings.

FIG. 1 is a system configuration diagram of a data processing system commonly applied to the present invention and a conventional input/output control method. Figure 2 shows data (files) from a magnetic disk unit (hereinafter referred to as DKU) in the conventional input/output control method.
FIG. 2 is a conceptual diagram showing the operation of reading and writing to a magnetic tape unit (hereinafter referred to as MTU).

The logical copying of files between the conventional DKU and M T U li is taken as an example of copying from DKU to MT[J.
This will be explained with reference to Fig. 1C and Fig. 2.

When a read command is output from the CPU 1 to the DKU 5, the magnetic disk control device (hereinafter referred to as DKC) 4
Sends the necessary information (7 isles) to KU5 or a seek command to move the head to the stored position. When the seek operation of DKU5 is completed, DKC
4 is Data's lead command) Cloak is DKU5
Send to. When the DKU5 finds the beginning of the specified information (file), it transfers the information to the DKC4. D.K.
C4 uses DMA to send the information sent from DKU5 [C
The main memory (not shown) in PU1 is transferred. When the DKC 4 finishes transferring the necessary information, it generates an interrupt to the CPUI and notifies the CPU of the end of the read operation.

When the CPUI receives the DKU5 read operation completion notification,
Executes a write command for MTU3K.

The magnetic tape controller fi'e (hereinafter referred to as MTC) 2 is M
When a write command is sent to TU3, C
Receives information from PUI via DMA.

MTU3 starts feeding the magnetic tape, receives and writes more information than MTC2. When MTC2 finishes transferring the necessary information, it generates an interrupt to CPU1 and writes it.
Notify the end of the work.

The CPU 1 repeats the above series of operations as many times as necessary.

By the way, in general, D used in data processing systems
As is well known, the configuration of KU5 is shown in Figure 3(a), (
As shown in b), the IC has multiple disk plates and multiple tracks, and the data recording portion on the disk plate is divided into multiple circumferences (hereinafter referred to as tracks). , the same track is divided into multiple sectors. The data handled by the software is shown in Figure 3 (C), (
As shown in d) and (e), the minimum recording unit is a record, a collection of records is treated as a block, and a collection of blocks is treated as a file, and the files recorded on the DKU5 are as shown in Figures 3 and 5. As shown in Figure 4, they are recorded in physically continuous or discontinuous positions (logically continuous). Also, generally DKU5
The average seek time for MT
When accessing U3, it takes Fi 500ms on average to move the air transmission tag from a stopped state.

(Problems that the invention attempts to solve with the calendar method) In such a conventional method, the operation of logically copying a file from the DKLI to the MTU is a seek operation, a DK
DMA data transfer from U to CPU, interrupt processing, magnetic chip 7 running, DMA data transfer from CPU to M '1' U, and interrupt processing are repeated in this order, so it takes a lot of time to run the magnetic tape. It requires time of C.
There is a problem that the load on the PU becomes extremely heavy due to interrupt processing and the like.

As a result, there are problems in that the processing speed of the CPU becomes slow and the logical copy operation requires a very long time due to the operation of stopping and starting the magnetic tape.

In addition, if an error occurs when accessing the MTU, the number of interrupts increases as the magnetic tape is reversed and the DMA data transfer is corrected.
% of error blocks = processing for inclusion, and C
There is a problem that the load on the PU becomes heavy.

In addition, it is an object of the present invention to be able to reduce the load on the CPU, to perform a 7-aisle physical copy between the DKU and MTU via the main memory at high speed, and to reduce the load on the CPU.
An input/output system that allows retrying only by control in MTC when an error occurs (input/output system)1
Our goal is to provide a method for you.

(Means for Solving the Problems) For this purpose, the system of the present invention provides an input method for controlling logical copying operations via main memory performed between a magnetic tape device having a streaming function and a magnetic disk device. In the output control method, the main memory includes a plurality of data buffers each storing one block of transfer data, each buffer having an effective table length, table usability designation,
At least one table is provided for storing a next table referability designation, the number of blocks, the current block number, the table length of the next table, block information, the next table address, and an offset value for retrying in case of an error; The tape control device is provided with a sub-table for storing a copy of one of the tables in the main memory, and before the central processing unit reads a plurality of blocks of data from the magnetic disk device to the data storage.

f -7''# Before K, write 8 contents - C - 7・!
chaining the files and continuing reading from the magnetic disk device and issuing a write command to the magnetic tape control device, and the magnetic tape control device responds to the write command by writing the contents of the table in the main memory to the By writing the contents of the data buffer to the magnetic tape device based on the contents of the sub-table, the control in the magnetic tape control device can be performed without stopping the running of the magnetic tape and when an error occurs. The feature is that it is possible to retry only by

(Example) Next, an example of the present invention will be described in detail with reference to the drawings. An embodiment of the present invention is shown in FIGS. 1 and 5. FIG. In Figure 1, 1 is the CPU, 2 is the MTC, and 3 is the MTU14.
is DKC, 5 is DKU.

101 is an address register, 102 is a data register,
103 is a bus control circuit, 104 is a microprocessor,
105 is a ROM, and 106 is a RAM.

Reference numeral 107 indicates a device control circuit. In FIG. 5, 201 is an address counter, 202 is a data buffer, 203 is a data color buffer, 204 is a first-in first-out control buffer (hereinafter referred to as EIFO), and 205 is a control circuit.

FIG. 6 shows the relationship between n tables developed in the main memory on the CPUI, and FIG. 7 shows the structure of this table. In FIG. 7, the SPM dump area pointer indicates the start address of the main memory when the contents of the RAM 106 at the time of an error are transferred to the main memory, the effective table length indicates the size of the table itself, and the control information area indicates the size of the table itself. Indicates the control state, the block number indicates the number of blocks included in the table, the offset value indicates the number to skip the operation from block 1, the current block number indicates the block number that MTC2 is processing, and the next The table address of indicates the next table address to be referenced when the processing of one table is completed, the table length of the next table indicates the size of the next table to be referenced, and the /(sofa address is The range indicates the number of data to be transferred in that block, the remaining range indicates the remaining range at the end of the block's operation, and the status indicates the number of data to be transferred at the block's end. Store status.

FIG. 8 is a diagram showing an example of details of the control information area in the table, and FIG. 9 is a diagram showing an example of details of the control information area in the table, and FIG.
4 shows the block information of the table written to the FIFO 204. In FIG. 8, the reference symbol VT is “1”.
# indicates that this table can be used, and K indicates that it cannot be used when it is 0'', and the reference symbol TM is 1''.
When , it indicates that the table chain ends at this table), and when the reference symbol CP is '1#, it indicates that this table has been processed normally, and the reference symbol ER
When is 1#, it indicates that an error occurred while processing this table, and when the reference symbol (T) is 1'', it indicates that the value set in this table is inappropriate.

The logical copy operation of files from the DKU 5 to the MTU 3 will be described below with reference to FIGS. 5, 6, 7, 8, and 9.

First, the CPU 1 sequentially transfers the seven files to be copied from the DKU 5 to the main memory. DKU5 for a suitable number of blocks
After reading from , a table for starting MTU is generated in the main memory. When table generation is completed, VT7. in the control information area of this table. F (1)
1#, and specifies the start address of the table (XXX in FIG. 6) to MT02 to start it.

When the MT02 receives the start address XXX of the table, the microprocessor 104 returns the start address
9. Retrieve the table specified by from main memory. RAM1
Store in 06. Next, the VT7 lag in this table is “
1", then write block number "1" to the current block number area of the table in RAM 106 and the current block number area of the table in main memory. 1, at this time, the offset value is specified in the table. If so, the block number will be Offseratoy Takumi.

Next, the microprocessor 104 stores block information as shown in FIG.
05 is given an instruction to start the transfer.

The control circuit 205 outputs the Shibasofa address and range from the FIFO 204, and inputs each to the address counter 20.
1 and data counter 203, MTU3 K
Send a write command to.

The MTU3 starts running the magnetic tape, and when it becomes ready to receive data, makes a data request to the control circuit 205. When the control circuit 205 receives this data request, the address register 101 that holds the address from the address counter 201 and the path control circuit 103 assist the control circuit 205 from main memory → data register 102 → data buffer 202 → control circuit. 205→MTU 3 route) to perform data transfer. At this time, the address counter 201 is incremented by 1 every time one byte is transferred, and the data counter 203 is incremented by -1.

When the data counter 203 becomes '0'', the control circuit 205
generates an interrupt to the microprocessor 104 to indicate the end of one block transfer (even if the data counter 203 is ←0, if an error occurs, an interrupt is generated to the microprocessor J), and if there is no error, the buffer address of the next block is sent from the PIFO 204. Take out the microwave and take out the address counter 20.
1. Set the data counter 203 and start transferring the next block. If there is an error, do not proceed.

On the other hand, when the microprocessor 104 receives an interrupt indicating the end of the block, it receives the end status from the control circuit 205 and writes it into the block status area of the table in the main memory. Also, if there are 7 errors in the status, 106 is added to RA8 and the current block number area of the table on the main formula +X is increased by +1. If there is an error in the status, the current block number is +1 and there is no λ. The control circuit 205 determines whether an error occurs or all blocks? Repeat the above operation until the transfer is completed.

MTU3 Fi... After writing i blocks, the IRQ which is the gap between the blocks is written, so if the next write command is received while writing this IRQ, the magnetic tape will continue to run without stopping. and write the data. When the microprocessor 104 finishes processing all blocks of the table, it sets the CP7 lag in the control information area of the table in the main memory (if an error occurs, it sets the ER flag or E'EL flag). I
Set the T7 lug. ) interrupts the CPUI.

Next, referring to the next table address area and table length of the next table in RAM 106, the next table is transferred to the main memory and stored in QRAM 106. If an error occurs or the TM flag in the control information area is If set to 1, the next table will not be referenced. ) Repeat the same operation.

On the other hand, when the CPUI receives an interrupt from MTC'2, it checks the ER, flag and CP flag in the control information area of the existing table, and ER flag = ''0# and CP flag = 1.
In this case, update (or delete) the existing table. ER7
When lag = 61'', set the current block number of the existing table to the offset value of the existing table, set the current block number, ER flag, and IT flag to ``0'', and set the starting address on the main memory of the existing table. Retry processing can be performed simply by instructing the MTC2 and activating it.

When an error occurs, MTC2 issues a command to MTU3 to pack two blocks from the block where the error occurred, and then issues a command to move forward one block.
Position the magnetic tape at the beginning of the error block, and
Wait for command from UI.

In addition, the CPU can determine the processing status of the table by looking at the current block number area of the table, so if necessary, read the file from DKU5 and set the MTU
The speed of writing to 3 can be adjusted by changing the size and number of tables to be chained thereafter. What has been explained above is based on FIG. 10, which is a conceptual diagram of a 7-isle logical copy operation from DKU5 to MTU3, and an example of 040 between CPUI-MTC2-MT03. The understanding will be further deepened by referring to FIG. 11, which is a flow diagram, and FIG. 12, which is a flow diagram showing an example of processing within the MTC 2.

(Effects of the Invention) According to the present invention, by employing the configuration described above, it is possible to reduce the number of interrupts to the CPU by the number of blocks set in the table, thereby reducing the load on the CPU. Perform logical copying of 7 isles at high speed,
Moreover, there is an effect that retry can be performed without reorganizing the error temporary table.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram common to the prior art and the present invention.
Figure 2 is a conceptual diagram showing a logical copy of a file in the prior art, Figures 3 (a) and (b) are conceptual diagrams of the DKU head, track, and sector, and Figures 3 (C), (d) ( e) is a file configuration example, FIG. 4 is a diagram showing logical copying from DKU to MT, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIGS. 6, 7, and 8 are FIG. 9 is a conceptual diagram of block information stored in FIFO; FIG. 10, FIG. 11, and FIG. 12 are conceptual diagrams of the operation of an embodiment of the present invention. It is. 1...CPU, 2...MTC, 3...
...MTU14...DKC,5...
・DKU, 101...Address register, 10
2...Data register, 103...Bus-based all DDK, 104...Microprocessor, 105--ROM1106. Old,,RA
M, 107...Device control circuit, 201...
...address counter, 202...data buffer, 2o3...group data callan', 204...
...FIFOl 205...music/control circuit. Agent Patent Attorney Shinso Uchihara 45 Z 纂6 Lessons Figure 9

Claims (1)

[Claims] In an input/output control method for controlling a logical copying operation via a main memory performed between a magnetic tape device and a magnetic disk device having a streaming function, each of the main memories includes: Multiple data buffers that store one block of transfer data, each with an effective table length, table usability specification,
At least one table is provided that stores a next table referenceability designation, the number of blocks, the current block number, the table length of the next table, block information, the next table address, and an offset value for retrying in the event of an error; The tape control device is provided with a sub-table for storing a copy of one of the tables in the main memory, and the central processing unit updates the table each time a plurality of blocks of data are read from the magnetic disk device into the data buffer. Writing the contents to chain the table and continuing reading from the magnetic disk device, and issuing a write command to the magnetic tape control device, and the magnetic tape control device writes the main memory in response to the write command. By writing the contents of the data buffer to the magnetic tape device based on the contents of the sub-table, it is possible to prevent the magnetic tape from stopping when an error occurs without stopping the running of the magnetic tape. An input/output control method characterized by being able to perform retrials only by controlling the tape control device.