JPS6198468A - data transfer system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time by DMA-transferring directly data necessary for a host OS between system memories and other data between buffers. CONSTITUTION:A DMAC2 controls data from an I/O device 5 composed of a drive 3 and its interface circuit 4. The data necessary for the operation system (OS) is directly DMA-transferred to the system memory 7 and other data is DMA-transferred to the buffer memory 6.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a data transfer system between a host and an input/output device. Data transfer system in case (
(Regarding.

[Background of the invention]

Regarding the number of bytes per sector (well, conventionally there has been the following problem, and it has not been possible to uniquely determine the number of bytes per sector.

Table 1 Table 1 shows the storage capacity per track for a 5-inch hard disk, and the sector length is 1024.
It can be seen that the memory on the disk can be used effectively when using bytes. However, in the case of C, on the system memory,
Even if the required data block is 256 bytes, 1024 bytes of data, which is four times as much, will be transferred to the system memory, resulting in a loss of 768 bytes of data transfer time. Therefore, in order to shorten the required data transfer time, it is better to have a smaller number of bytes per sector (sector length).

In reality, the physical sector length of the input/output device is determined by taking both of these into account and making it match the sector length managed by O8.

In addition, as related to the data transfer system, for example, Japanese Patent Application Laid-Open Nos. 58-169658 and 58-5867
No. 58-146953, etc.

[Purpose of the invention]

The purpose of the present invention is to determine the sector length managed by O8 of the host,
The purpose is to reduce the loss of data transfer time on average when the physical sector lengths of input/output devices are different.

[Summary of the invention]

In order to achieve the above object, the present invention performs DMA transfer of data blocks required by the host O8 directly between system memories without going through a buffer memory, and transfers other data blocks between buffer memories using DMA transfer.
By performing A transfer, we aim to shorten the data transfer I@darkness.

[Embodiment J of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the data transfer system l, /j in the present invention.
') 'z-ゝtsu'a composition 6mo'a6・middle 1
The central processing unit (CP(J) 1 performs memory management under the control of the O8 (operating system). The direct memory access control circuit 1) MAC) 2 controls the drive 38 and its interface circuit (I/F). 4
It controls data transfer between the input/output device 5 consisting of the buffer memory 6 or the system memory 7.

The following figures show the state of DMA transfer when the physical sector length of the input/output device is 1024 bytes and the sector length managed by O8 is 256 bytes.
61 has a storage capacity of one sector of input/output controller,
Normally, this buffer memory 61 ((When a data block of 1 sector of remaining input/output I is transferred from D to IA and O8 requires 256 bytes from 512 Satsuji onwards in buffer memory 61, %K ``l'': The present invention transfers 256 bytes from address 512 on the loaded buffer memory 61 to a predetermined location in the system memory t!f71 IC data.The present invention transfers 256 bytes from address 512 on the buffer memory 61 to the buffer memory 61 by DMA to the buffer memory 610512, and requires O8. The next 256 bytes are stored directly in the system memory, not in the buffer memory 61, but in a predetermined location N71K D M
A Transfer. The remaining 256 bytes are DMA-transferred to a predetermined location in the buffer memory 61.

This method can reduce the data transfer time by 256 bytes compared to the method of DMA-transferring all one sector of the input/output device to the buffer memory 61 and then transferring the data to a predetermined position 71 of the stem memory. .

FIG. 3 is a diagram showing the state of DMA transfer in the case of continuous sectors. The logical sector number managed by O8 is 3 to 8, and the corresponding physical sector number of the input/output device is 1 to 3.
The case will be explained below. (a) The data block of logical sector number 3 managed by the OS corresponds to 256 bytes after 768 bytes of physical sector number 1 of the input/output device,
After 768 bytes are DMA transferred to the buffer memory 62, 256 bytes are DMA transferred to a predetermined location 72 in the system memory. (b) Logical sector numbers 4 to 7 managed by o s correspond to one sector of physical sector number 2 of the input/output device, and 1024 bytes are directly stored in a predetermined location 73 of the system memory without going through the buffer memory 62. D.M.A.
Forward. (c) Logical sector number 8 managed by the OS corresponds to the first 256 bytes of physical sector number 3 of the input/output device, and after DMA transfer of 256 bytes to a predetermined location 74 of the 7-stem memory, the buffer memory 62 DMA transfer the remaining 768 bytes.

In this case, the input/output device is physically accessed only three times, and if the physical sector length of the input/output device matches the sector length (256 bytes) managed by O8 (six times)
Compared to , the maximum sector length difference is 1/4 (25
6/1024), the number of accesses can be reduced.

In the case of (C), the first 256 bytes of data in the buffer memory 62 are the first 256 bytes of data in the state of (a), and if there is enough data transfer time, 1
It is preferable to transfer the data to a predetermined location 74 in the system memory 62 overnight after DMA transfer to the buffer memory once.

FIG. 4 shows a state in which the data block with logical sector number 2 managed by O8 is read after the data block with logical sector number 1 is read out. (The data block with logical sector number 1 managed by alO8 corresponds to 256 bytes after physical sector number 10256 bytes of the input/output device, and 256 bytes are stored in the buffer memory 63.
After the M A transfer, the predetermined location [75
256 bytes 1) After MAA transfer, DM the remaining 512 bytes to a predetermined location in the buffer memory 63.
A Transfer. (b) Next, regarding the data block with logical sector number 2 managed by O8 (well, we have already written 2 in (a))
In this case, the number of times the input/output device is accessed is 1. As explained in FIG. 3, the number of accesses can be reduced to a maximum of 1/4. In this case as well, if there is sufficient data transfer time, it is preferable to perform DMA transfer once to the buffer memory 63 and then transfer the data to a predetermined location 75 in the system memory.

FIG. 5 is a diagram showing a state in which a data block (256 bytes) located at a predetermined location 77 in the system memory is loaded into an input/output device. A case will be described in which a data block (256 bytes) at a predetermined location (i.e. 77) of the system memory is written to the 256 bytes and subsequent 256 bytes of logical sector number 1 managed by O8, that is, physical sector number 1 of the input/output device. (a) DMA transfer the sector with physical sector number 1 of the input/output device to the buffer memory 64. (b) Next (f) Transfer the data block (256 bytes) at the predetermined position 77 of the system memory to the buffer memory address 640256. After that, 256 bytes of data are transferred.After that, data 102 of the buffer memory 64 is transferred.
DMA transfer 4 bytes to input/output device.

The present invention reduces the data transfer time by 256 bytes by directly transferring the data block (256 bytes) located at a predetermined location 77 in the system memory to the input/output device without going through the buffer memory 64. This method is particularly effective in the case of continuous sectors, and can reduce the number of accesses by input/output devices. Of course, for data blocks in the system memory that exceed the physical sector length of the input/output device, DMA transfer from the input/output device to the buffer memory as in (a) is no longer required, and the 1024 bytes on the system memory are directly transferred to the input/output device. D.M.A.
Can be transferred.

FIG. 6 is a flowchart showing specifically how address switching in DMA transfer is performed. Here, we will take the case explained in Figure 3 as an example.
A flowchart of the read function will be explained.

■ Check which physical sector number of the input/output device corresponds to the logical sector number managed by O8. In the case of FIG. 3, the physical sector numbers are 1-3.

(2) Separate the area for DMA transfer to the system memory from the logical sector number and the area for DMA transfer to the buffer memory. In the case of Figure 3, the DMA transfer to the buffer memory is the first 768 bytes of physical sector number 1 and the last 768 bytes of physical sector number 2, and the DMA transfer to the system memory is the first 768 bytes of physical sector number 1. last 256 bytes, physical sector number 201024 bytes,
This is the first 256 bytes of physical sector number 3.

■ Execute DMA transfer. In the case of FIG. 3, the procedure is specifically as follows.

■ Access physical sector number 1 of the input/output device and make it possible to read data from the input/output device.

o Set the buffer memory start address (
0 address) and the number of data transfers (768 bytes).

(4) Operate DMAC and perform DMA transfer.

Set the system memory start address (0) to ODMAC.
address) and the number of data transfers (256 bytes).

@ Operate DMAC and perform DMA transfer.

O Accesses physical sector number 2 of the input/output device and makes it possible to read data from the input/output device.

◎ Enter the next start address of the system memory (2564 locations) and the number of data transfers (1024 bytes) in the DMAC.
Set.

@ Operate DMAC and perform DMA transfer.

Access the physical sector number 3 of the O input/output device and make it possible to read data from the input/output 1 device.

4) Input the next start address of the system memory (address 1280) and the number of data transfers (256
bytes).

Operate mouth DMAC and transfer DMA.

α ■ Set the start TI of the buffer memory to DMAC, set address C256 as the data transfer number, and set it as 7.
Set 68 bytes.

(, 9 operates DMAC and performs DMA transfer.

The DMA transfer is executed through the O-port procedure.

When writing, one sector is read from the input/output device once and DMA transferred to the buffer memory, and
The flowchart is basically the same as that in FIG. 6, except that the direction of MA transfer is reversed.

The software corresponding to the flowchart described here is executed within the BIO8 (basic input/output system) routine, is not under the control of O8, and functions independently as an input/output drive routine.
35 Ru. The O8 merely uses this l3IO8 as a subroutine. [Effects of the Invention] As explained above, according to the present invention, the logical sector length managed by the O8 and the physical sector length of the input/output device are If the data blocks are different, data blocks required by O8 are transferred directly to the system memory IJKDMA without going through the buffer memory, and other data blocks are transferred by DMA to the buffer memory, reducing data transfer time loss. I can do it.

Since the physical sector length of the input/output device can be determined independently of the logical sector length managed by O8, the sector length that maximizes the effective storage capacity of the input/output device can be selected.

Since the number of accesses to the input/output device is reduced, there are effects such as the ability to reduce the equal constraint average access time.

In addition, these effects also apply to D
A similar effect can be obtained by simply reversing the direction of MA transfer.

[Brief explanation of drawings]

Figure 1 is a hardware block diagram constituting an embodiment of the present invention, and Figures 2 to 4 show the states of the buffer memory and system memory at the time of reading. 5 is an explanatory diagram for explaining the states of the buffer memory and stem memory at the time of writing,
Figure 6 is a flowchart for explaining the software procedure at the time of reading. 1... Central processing unit 2... 1) M AC 5... Input/output device 6... Buffer memory 7... System memory 61-64... Buffer memory 71-77... System Memory Feng)

Claims (1)

[Claims] 1. A central processing unit, a system memory, a buffer memory, a direct memory access control circuit,
In a data transfer system comprising an input/output device having a sector length larger than the sector length managed by an operating system, when the operating system reads a data block from the input/output device,
Only necessary data blocks are DMA-transferred directly onto the system memory without going through the buffer memory, and if there are other data blocks, they are DMA-transferred onto the buffer memory; conversely, the operating system When writing a data block, only the necessary data block on the system memory is directly written to the input/output device without going through the buffer memory.
and, if there is any other data block, it is transferred by DMA from the buffer memory to the input/output device.