JPS62113256A - Bus control system - Google Patents

Abstract

PURPOSE:To prevent the priority of a DMA request from being decided unconditionally by providing a system capable of being used exclusively by a DMA means which sends its output in the output period of a DMA request order bus hold signal. CONSTITUTION:A DMA control part, plural DMA means 10-12, and a system bus are provided. The DMA control part 1 checks a DMA request order but hold signal on a signal line 21 at any time and keeps on outputting the DMA request order signal outputted to a bus signal line 20 when detecting '0'. At this time, a system bus signal line 22 composed of an address bus and a data bus is controlled by a DMA means which outputs the DMA request order bus hold signal to the signal line 21 and the DMA request order bus hold signal is set to '1' to release the system bus, so that a DMA control part begins to send out a new number to the bus signal line 20. Consequently, the bus use priority of the DMA means is easily varied.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control system having a plurality of direct memory access (DMA) means.

(Prior Art) Conventionally, a system having a DMA means issues a DMA request signal to a DMA control unit, receives a DMA permission signal for itself from the DMA control unit, and uses a data bus and an address bus. , the number of pairs of DMA request signals and DMA grant signals is determined by the number of pairs of DMA request signals and DMA grant signals present in the system.
There were as many means as A.

(Problems to be Solved by the Invention) In the conventional bus control method described above, the DMA request signal and the
Since the number of pairs with the MA permission signal is equal to the number of DMA means, the number of signal lines increases as the number of DMA means increases, and in a system in which each DMA means is packaged, the number of mounting slots is usually limited. l) The disadvantage is that the priority of MA requests is uniquely determined.

An object of the present invention is to provide a DMA priority bus for giving a DMA request priority from a DMA control unit to a DMA means;
Data on the DMA ranking path and fixedly given to itself 7
By outputting a DMA request priority bus hold signal from the DMA means at the time when the tDMA priority number matches, the above drawback is eliminated, and the priority of the DMA request is uniquely determined without increasing the number of signal lines. The object of the present invention is to provide a path control method configured to prevent such occurrences.

(Means for Solving the Problems) A path control system according to the present invention is configured to include a DMA control section, a plurality of DMA means, and a 7-stem path.

The DMA control unit is for sending out a plurality of DMA ranking signals indicating DMA request rankings.

The plurality of DMA means compares whether or not the DMA order number matches its own DMA order number, and outputs a DMA request order bus hold signal when the two match.

The system bus can be exclusively occupied by the DMA means sending out the above output while the DMA request priority bus hold signal is being output.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a system for implementing the path control method according to the present invention. In FIG. 1, l is a DMA control unit, and 10 to 12 are DMs, respectively.
This is means A.

FIG. 2 is a time chart showing an example of a signal representing a DMA request priority number on the path signal line 20 and a DMA request priority bus hold signal on the signal line 21.

In FIGS. 1 and 2, the DMA request priority number (8 bits) is sent onto the DMA control unit formula signal line 20 at the timing shown in FIG. It is input to means lO-12. Each of the DMA means 10 to 12 is given a different DMA request order number, and when the number on the bus signal line 20 matches its own DMA request order number, the corresponding DMA
The means outputs a DMA request priority bus hold signal onto the signal line 21.

The DMA control unit constantly checks the DMA request priority bus hold signal on the line 21, and if %01'ie is detected, the D output on the path signal line 20 at this point
Continue to output the MA request priority signal. At this time, the system bus signal line 22 consisting of an address bus and a data bus
can be controlled by the DMA means that outputs the DMA request priority bus hold signal on the signal line 21. By setting the DMA request priority bus hold signal to %1, the system bus is released, and the DMA control section A new number begins to be sent to the bus signal line 20.

(Effects of the Invention) As explained above, the present invention can realize a reduction in the number of DMA request signal lines by controlling the DMA path usage right by the path, and at the same time, the number of DMA request signal lines can be reduced. This has the advantage that the degree of freedom in mounting position can be increased, and the path use priority of the DMA means can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a system implementing a path control method according to the present invention. FIG. 2 is a time chart showing an example of a DMA request priority number and a DMA request priority bus hold signal. lφ...DMA control unit 10-12...-DMA means 20-22/11th signal line

Claims (1)

[Claims] a DMA control section for sending out a plurality of DMA order signals indicating DMA request orders;
A plurality of DMA means for comparing whether or not they match with the MA order number and outputting a DMA request order bus hold signal when the two match, and a period during which the DMA request order bus hold signal is outputted. and a system bus which can be exclusively used by the DMA means sending out the output.