JPS621231B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-interval timer that repeats a cycle timer operation using a plurality of timer times as one cycle.

Recently, electronic wristwatches, small electronic computers, and the like have become increasingly multifunctional, and products have been commercialized that incorporate a so-called timer function that sounds after a set time has elapsed. And as for this timer function,
A multi-interval timer is being considered in which a plurality of timer times, such as ``30 minutes'' and ``10 minutes'' are set, and a sound is generated each time the ``30 minutes'' and ``10 minutes'' elapse. This multi-interval timer is
For example, it is used in track and field practices where the cycle of practicing for 30 minutes, taking a break for 10 minutes, and so on is repeated several times. However, when used in this way, if you miss the signal, you may have to take a long time to practice or take breaks, or you may not know which cycle of practice you are in. There was a risk that this would interfere with planned practice.

The present invention has been made in view of the above circumstances, and its purpose is to provide a multi-interval timer that can easily determine which cycle it is in by clearly indicating the number of cycles.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram of an electronic wristwatch to which the present invention is applied. In the figure, reference numeral 1 denotes an oscillation circuit that generates a reference frequency signal, and the reference frequency signal is divided into a one-second cycle signal by a frequency dividing circuit 2 and sent to a clock circuit 3. This clock circuit 3 generates "hour" as time information based on a signal with a period of 1 second sent from the frequency dividing circuit 2.
This is used to obtain the "minute" and day of the week information. These time information and day of the week information are supplied to the liquid crystal display device 5 via the display switching circuit 4, and are displayed digitally or analogously. On the other hand, in the figure, reference numeral 6 denotes a switch operation unit including various switches to be described later, and operation signals from each switch are given to a control unit 7. This control unit 7 receives a signal 1P/1S with a period of 1 second output from the clock circuit 3.
is given. Further, the control unit 7 supplies the plurality of timer time setting value information _a1 obtained by operating the switch operation unit 6 to the storage unit 8, and also sets the repetition period of the plurality of timer time setting value information to one cycle. When the cycle is repeated, the cycle number setting value information A ₂ that sets how many times this cycle is repeated and the cycle number count value information A ₃ that counts how many times this cycle is repeated are set as the above timer time setting value. It is supplied to the display switching circuit 4 together with information _a1 . The storage section 8 stores timer time setting value information _a1 given from the control section 7, and is read/written in accordance with read/write signals given from the control section 7.
Receive writing instructions. The timer time setting value information read from the storage section 8 is supplied to the down counter 9. This down counter 9 is sequentially subtracted every minute according to the output signal of the AND circuit 10. One input terminal of the AND circuit 10 is supplied with a signal 1P/1M with a period of one minute output from the clock circuit 3, and the other input terminal of the AND circuit 10 is supplied with a signal 1P/1M from the control section 7. A timer start signal is provided to be output. The contents of the down counter 9 are supplied to the display switching circuit 4. The display switching circuit 4 is supplied with display switching control signals Q ₁ to Q ₃ output from the control section 7, and selectively outputs input information according to these display switching control signals Q ₁ to Q ₃ . , liquid crystal display section 5
supply to. The liquid crystal display section 5 has a display 5a that displays the time and time information, and a display 5b that displays the day of the week and the number of cycles. The contents of the down counter 9 are supplied to the "0" detection circuit 11, and when the contents reach "0", the "0" detection circuit 11 gives a one-shot pulse "0" detection signal to the control section 7. . In addition, the control unit 7 sends a voice selection signal A ₁ to specify a short tone, a long tone, or a continuous tone.
_A3 is outputted and given to the alarm control circuit 12. The alarm control circuit 12 selectively outputs an alarm control signal based on the audio selection signals A ₁ to A ₃ and supplies it to the buzzer circuit 13 to drive it.

FIG. 2 is a circuit configuration diagram showing details of the control section 7 and storage section 8. As shown in FIG. In the figure, _S1 is a timer time setting switch, _S2 is a timer time writing designation switch, _S3 is a timer master switch, _S4 is a safety switch for timer time setting, and _S5 is a cycle number setting switch. , these switches _S1 to _S5 are provided in the switch operation section 6.

The operation signal of the timer time setting switch _S1 is applied to the one-shot circuit 701, which causes the one-shot circuit 701 to output a one-shot pulse and increment the contents of the sexagesimal counter 702. Further, the operation signal of the write designation switch S ₂ causes the AND circuit 704 to output a one-shot pulse via the one-shot circuit 703, and the one-shot pulse from the AND circuit 704 is sent to the storage section 8 and is also sent to the quinary counter 705. Advance the content of The contents of this counter 705 are:
The signal is supplied to a decoder 706 and decoded into signals of "0" to "4". On the other hand, the contents of the counter 702 are sent to the storage section 8 and are sent to the five AND circuits 8.
The signals are supplied to input terminals 01 to 805, respectively. Further, the output signal of the AND circuit 704 is sent to the storage section 8 as a write designation signal, and is given to the input terminals of each of the AND circuits 801 to 805 as a gate control signal. Furthermore, the decoder 706
The signals "0" to "4" are sent to the storage section 8 and given to the input terminals of the corresponding AND circuits 801 to 805 as gate control signals. The output contents of each of these AND circuits 801 to 805 are as follows.
The data is supplied to and written into the corresponding storage areas 806-810. The contents of the counter 702 are supplied to the display switching circuit 4 as timer time setting value information _a1 .

Further, the operation signal of the timer master switch _S3 causes the one shot circuit 708 to output a one shot pulse, and the binary flip-flop 70
9 to the T input terminal. This binary flip-flop 709 normally outputs a "1" signal from its side output terminal, and inverts its output state when a one-shot pulse is applied to its T input terminal. This flip-flop 70
The side output signal of 9 is given to one input terminal of the AND circuit 710, and the Q side output signal is sent out as the display switching control signal _Q2 , and the output signal of the Q side is sent to the display switching circuit 4.
given to. The one shot pulse from the one shot circuit 708 is applied to the other input terminal of the AND circuit 710 as a gate control signal. The output signal of the AND circuit 710 is applied to the set side input terminal S of the RS type flip-flop 711 and also to one input terminal of the OR circuit 712. Flip-flop 7 above
The Q side output signal of 11 is given to one input terminal of the AND circuit 713, and the AND circuit 7
The other input terminal of 13 is connected to the above “0” detection circuit 1.
A “0” detection signal from 1 is given. This AND circuit 713 provides its output signal to the other input terminal of the OR circuit 712. The output signal of this OR circuit 712 is sent to the storage section 8, and each AND circuit 81 corresponding to the storage areas 806 to 810
It is given to input terminals 1 to 815 as a read designation signal. Each of these AND circuits 811 to 815
are supplied with the contents stored in the corresponding storage areas 806-810, respectively. Further, the output signal of the OR circuit 712 is sent to the quinary counter 714.
is sent as the audio selection signal _A1 .

The contents of the counter 714 are supplied to a decoder 715 and decoded into signals of "0" to "4".
Signals "0" to "4" from this decoder 715 are sent to the storage section 8 and given to the input terminals of the corresponding AND circuits 811 to 815 as gate control signals. Each of these AND circuits 811 to 81
The output contents of 5 are supplied to the down counter 9 via the OR circuit 816. On the other hand, the counter 70
The contents of 5 and 714 are also provided to match circuit 716. This matching circuit 716 is a counter 70
When a match is detected between the contents of 5 and 714, a one-shot pulse match signal is output and the counter 717
is incremented and given to the alarm control circuit 12 as the audio selection signal _A2 , and also to the counter 714.
Clear the contents of. The contents of this counter 717 are sent out as cycle number count value information _a2 .

Further, the operation signal of the timer time setting safety switch _S4 causes the one shot circuit 718 to output a one shot pulse, and this one shot pulse is applied to the T input terminal of the binary flip-flop 719. This binary flip-flop 7
19 normally outputs a signal of "1" from the side output terminal, and when a one-shot pulse is applied to the T input terminal, the output state is inverted. This side output signal of the flip-flop 719 is applied to the counter 702 as a reset signal R, and also to the display switching circuit 4 as a display switching control signal _Q1 . In addition, the Q side output signal of the flip-flop 719 is applied to the other input terminal of the AND circuit 704, and is also applied to the display switching circuit 4 as the display switching control signal _Q3 , as well as to one input terminal of the AND circuit 720. The other input terminal of this AND circuit 720 is connected to a cycle number setting switch.
The operation signal of _S5 is applied via a one-shot circuit 721. The output signal of this AND circuit 720 is given to a counter 722;
Advance the contents of 22. The contents of this counter 722 are sent out as cycle number setting value information _a3 . The contents of the counters 717 and 722 are also provided to a matching circuit 723, respectively. When this matching circuit 723 detects a match between the contents of the counters 717 and 722, it sends out a matching signal as the audio selection signal _A3 and also outputs a matching signal from the flip-flop 71.
1 as a reset signal.

FIG. 3 is a circuit configuration diagram showing details of the display switching circuit 4. As shown in FIG. In the display switching circuit 4, the time information from the clock circuit 3 is supplied to an AND circuit 401, and the day of the week information is supplied to an AND circuit 404.
Timer time setting value information a ₁ from the control unit 7 is supplied to an AND circuit 402 , cycle number count value information a ₂ is supplied to an AND circuit 405 , and further cycle number setting value information a ₃ is supplied to an AND circuit 406 . The contents of down counter 9 are supplied to AND circuit 403. Further, the display switching control signal Q ₁ is sent to the AND circuits 401 and 404, and the display switching control signal Q ₂ is sent to the AND circuits 401 and 404.
is applied to AND circuit 402 via inverter 407 and also applied to AND circuit 406 via AND circuits 403 and 405 and inverter 408. Display switching control signal _Q3 is AND circuit 4
03 and 406 as gate control signals, respectively. The output contents of the three AND circuits 401 to 403 are sent out via the OR circuit 409 and supplied to the display 5a of the liquid crystal display section 5, and the output contents of the other AND circuits 404 to 406 are sent to the OR circuit 410. and is supplied to the display body 5b of the liquid crystal display section 5.

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 8. Since the flip-flop 719 whose output state is reversed by the operation of the safety switch _S4 normally outputs a signal of "1" from the side output terminal, the contents of the timer time setting counter 702 are cleared. At the same time, a display switching control signal Q ₁ is applied to the display switching circuit 4. Therefore, in the display switching circuit 4, the gates of the AND circuits 401 and 404 are released, so that the time information and the day of the week information from the clock circuit 3 are supplied to the liquid crystal display section 5, and as shown in FIG. 5
Time information such as "10:58" is displayed by a, and day information such as "Monday" is displayed by display 5b.

Next, when using the timer as an interval timer, operate the timer time setting safety switch _S4 . As a result, the output state of the flip-flop 719 is reversed by operating the switch _S4 , and a signal of "1" is output from the Q side output terminal, which is applied to the display switching circuit 4 as the display switching control signal _Q3 . .
Therefore, in the display switching circuit 4, the AND circuit 40
Since the gate of 2,406 is released, timer time setting value information _a1 and cycle number setting value information _a3 are supplied to the liquid crystal display section 5 and output for display. In this state, the timer time setting switch _S1 is operated to input setting value information. In other words, the switch
Since the operation signal of _S1 is given to the counter 702 via the one-shot circuit 701, the counter 70
The contents of 2 are incremented according to the number of times the switch _S1 is operated. Each time the counter 702 is incremented, it is displayed as timer time set value information _a1 on the liquid crystal display section 5 via the display switching circuit 4, so while looking at this display, select the desired value. You can enter a timer time, for example "15 minutes". By inputting this timer time "15 minutes", the counter 7
02, the numerical value "15" is counted as shown in FIG. 4a. In this state, the contents of each storage area 806 to 810 in the storage unit 8 are as follows.
As shown in Figure 4 a, "0, 0, 0, 0, 0"
, and the content of the counter 705 is "0"
It is becoming. The contents of this counter 705 are decoded by a decoder 706, and a signal of "0" is output from the decoder 706, which is applied to the AND circuit 801 of the storage section 8. After the input for the timer time "15" is completed, write designation switch _S2 is operated. The operation signal of this switch _S2 is sent to the AND circuit 70 via the one shot circuit 703.
given to 4. Since the AND circuit 704 is supplied with the Q output signal of the flip-flop 719 which has been inverted by the operation of the safety switch _S4 , the AND circuit 704 outputs a one-shot pulse in accordance with the operation of the switch _S2 . The output signal of the AND circuit 704 is sent to the storage unit 8 as a write designation signal, and the gate of the AND circuit 801 is released. Therefore, the content of the counter 702, that is, "15" is passed through the AND circuit 801 to the first
The data is sent to the second storage area 801 and written as shown in FIG. 4b. Further, the output signal of the AND circuit 704 increments the contents of the counter 705. Therefore, the contents of the counter 705 are counted as "1", as shown in FIG. 4b. and decoder 7
06 decodes the contents of the counter 705 and outputs a signal of "1", which is applied to the AND circuit 802 in the storage section 8.

After setting the timer time "15 minutes" in this way, set the next timer time. That is, when the timer time, for example "10 minutes" is input by operating the switch _S1 , the contents of the counter 702 are counted by "10" as shown in FIG. 4c.
Then, when you operate switch S ₂ , the counter 70
As shown in FIG. 4d, the content "10" of 2 is written to the second storage area 807, and the content of the counter 705 is counted to "2". Similarly, when timer times such as "5 minutes" and "20 minutes" are continuously input, as shown in FIG. , counter 7
As for the contents of 05, "4" is counted as shown in FIG. 4e.

Next, the cycle number setting value information is set by operating the cycle number setting switch _S5 . The operation signal of this switch _S5 is applied to an AND circuit 720 via a one-shot circuit 721. This AND circuit 720 has a flip-flop 719 which is inverted by operation of the safety switch _S4 .
Since the Q side output signal of is given, AND circuit 720 outputs according to the operation of switch _S5 .
The output signal of this AND circuit 720 is
22 contents. If the cycle number setting value information is, for example, "4 times", then the counter 7
22 counts "4", and this value 4 is counted by the AND circuit 406 and the OR circuit 410 of the display switching circuit 4.
, and is displayed by the fourth display, that is, the display corresponding to Wednesday.

With the timer time and number of cycles set in this way, the timer start switch is
When _S3 is operated, a one-shot pulse is output from the AND circuit 710, and the flip-flop 711
is set and outputs a signal of "1" from its Q side output terminal, which is applied to the AND circuit 713. Further, the output signal of the AND circuit 710 is sent to the storage unit 8 via the OR circuit 712, and
815. Note that since the initial value of the counter 714 is "0", the decoder 71
5 outputs a “0” signal, and AND circuit 8
It is given to 11. Therefore, the AND circuit 81
1 is gated by the output signal of the OR circuit 712. Therefore, the first storage area 80
6, that is, "15", is supplied to the down counter 9 via the AND circuit 811 and the OR circuit 816, and as shown in FIG. The contents of 9 are sent to the display switching circuit 4. The output state of the flip-flop 709 is inverted by operating the switch _S3 , and the Q side output signal is sent to the display switching circuit 4 as the display switching control signal _Q2 . Since the display switching control signal Q ₃ is given to _the display switching circuit 4, the AND circuits 403 _{and 4}
05 is released, the content of the down counter 9 is "15", and the content of the counter 717 is "0", which is the OR circuit 4.
09 or 410 to the liquid crystal display unit 5, and is displayed as shown in FIG.

On the other hand, the output signal of the OR circuit 712 increments the content of the counter 714 to "1" and is applied to the alarm control circuit 12 as the audio selection signal _A1 , as shown in FIG. 5a. This sound control circuit 12 gives a sound control signal to the buzzer circuit 13 in accordance with the audio selection signal _A1 , and outputs a sound accompanying the timer start, for example, a short sound "beep" at the time of start, as shown in FIG. let

Then, the content "15" written in the down counter 9 is subtracted by -1 minute in accordance with the signal 1P/1M of 1 minute period given from the clock circuit 3 via the AND circuit 10. The result of this subtraction is displayed on the liquid crystal display section 5 via the display switching circuit 4, and is also supplied to the "0" detection circuit 11, where it is determined whether or not it is "0". As a result, when it is determined to be "0" by the above-mentioned subtraction, a "0" detection signal is given to the control section 7. This "0" detection signal is given to the AND circuit 713 of the control section 7, and the other input terminal of this AND circuit 713 is given the set signal of the flip-flop 109, which is in the set state when the start switch _S3 is operated. Therefore, AND circuit 7
An output signal is obtained from 13 and applied to an OR circuit 712. The output signal of this OR circuit 712 is
It is applied to each AND circuit 811 to 815 in the storage section 8 . At this time, since the decoder 715 is giving a signal of "1" to the AND circuit 812 in accordance with the content "1" of the counter 714, only the AND circuit 812 is gated, and the gate of the second storage area 802 is released. The content "10" is supplied to the down counter 9 via the AND circuit 812 and the OR circuit 816, and "10" is written in the down counter 9 as shown in FIG. 5b. On the other hand, the output signal of the OR circuit 712 increments the contents of the counter 714 to "2" as shown in FIG. 5b. Also, OR circuit 7
The output signal No. 12 is given to the sound control circuit 12 as the audio selection signal _A1 , and drives the buzzer circuit 13 to output a short sound "pi" as shown in FIG.

Similarly, the content "5" of the third storage area 808 and the content "20" of the fourth storage area 809 correspond to the content "0" of the down counter 9, as shown in FIGS. 5c and d. It is written sequentially each time. The counter 714 is also sequentially incremented. At this time, a match circuit 716 determines whether the contents of the counter 714 match the contents of the counter 705 or not. As a result, when a match is detected, it is found that one cycle of time has elapsed, and a match signal is given to the counter 717 to increment its contents.
The contents of 17 are supplied to the liquid crystal display section 5 via the display switching circuit 4 as cycle count value information _a2 ,
Displayed and output. On the other hand, the coincidence signal outputted from the coincidence circuit 716 is sent to the counter 714, its contents are cleared as shown in _FIG . Therefore, the alarm control circuit 12 sends an alarm control signal to the buzzer circuit 1 according to the audio selection signal _A2 .
3 to output a long tone (beep).

When one cycle is completed in this manner, the contents of the storage area 806 are transferred to the down counter 9 again, and as shown in FIG. 5e, "15" is written to the down counter 9, and the contents of the counter 714 are 1”. When two cycles are completed, the contents of the counter 717 are incremented,
It becomes "2". When the fourth cycle is completed and the contents of the counter 717 match the cycle number setting value information in the counter 722 in the match circuit 723, a match signal is output from the match circuit 723, and the flip-flop 711 is reset. It is given to the alarm control circuit 12 as the audio selection signal _A3 . Therefore, the sound control circuit 12 drives the buzzer circuit 13 in response to the audio selection signal _A3 to output a continuous sound (beep, beep, beep, beep, etc.).

As mentioned above, a short sound is emitted when the timer starts and when the timer time has elapsed, the number of cycles is also displayed, a long sound is emitted every time one cycle is completed, and a continuous sound is emitted at the end. By seeing or hearing these, you can know the number of cycles.

Note that since the number of cycles is displayed on the display 5a of the liquid crystal display section 5, it is possible to easily know the progress state of the repetition cycle.
A digital display may be provided to display the information.

Further, in the above embodiment, the timer time is set in minutes, but it may be set in units of hours or seconds. Further, in the above embodiment, the content of the down counter, that is, the remaining time of each timer time is displayed, but the present invention is not limited to this, and the remaining time up to the last timer time can be displayed as appropriate. It's okay. Also,
Although the above embodiment is configured such that one cycle consists of a maximum of five timer times, the present invention is not limited to this, and a RAM (random access memory) can be used for the storage section 5, and a control A fixed storage device such as a ROM (read-only memory) may be used for the section.

As explained in detail above, the present invention displays the number of cycles in a multi-interval timer that repeats multiple timer periods multiple times, making it easy to know how many cycles have been repeated. I can do it. Therefore, it is particularly effective in cases such as track and field, where a cycle of 30 minutes of practice followed by 10 minutes of rest is repeated many times in a row.

[Brief explanation of the drawing]

The drawings show one embodiment of the invention.
1 is a circuit configuration diagram, FIG. 2 is a detailed circuit configuration diagram of the switch operation section 6, control section 7, and storage section 8 shown in FIG. 1, and FIG. 3 is a circuit configuration diagram of the display switching circuit 4. 4a to 4e are diagrams showing the contents of the storage unit 8 and counters 702 and 705 that change each time the timer time is set, and FIGS. 5a to 5e show the down counter that changes each time the timer time is read out. 9 and the counter 714, FIGS. 6 and 7 are display state diagrams, and FIG. 8 is a diagram showing a state in which a tone is sounded each time the timer time elapses. 6... Switch operation section, 7... Control section, 8...
Memory section, 9...Down counter, 11..."0"
Detection circuit, 12... alarm control circuit, 13... buzzer circuit.

Claims (1)

[Claims] 1. A timer time storage section in which a plurality of timer times are set and stored, and a plurality of timer times stored in the timer time storage section are read out in a predetermined order to repeat continuous timer operations. In a multi-interval timer, the timer means includes a notification sound generating means that generates a notification sound after each of the timer times stored in the timer time storage section elapses; A multi-interval timer comprising: a counting means for counting the number of cycles in which one cycle consists of consecutive timer operations; and a display means for displaying the number of cycles obtained by the counting means.