JPS6213032U - - Google Patents
Info
- Publication number
- JPS6213032U JPS6213032U JP10425185U JP10425185U JPS6213032U JP S6213032 U JPS6213032 U JP S6213032U JP 10425185 U JP10425185 U JP 10425185U JP 10425185 U JP10425185 U JP 10425185U JP S6213032 U JPS6213032 U JP S6213032U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- reversible
- preset counter
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002441 reversible effect Effects 0.000 claims description 7
- 230000004397 blinking Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第1図はこの考案によるデジタルスイツチの一
例を示す側面図、第2図はこのデジタルスイツチ
の一例を示す回路図、第3図は動作状態表示器の
駆動選択回路の一例を示すブロツク図、第4図は
このデジタルスイツチ回路における入力禁止回路
の一例を示すブロツク図、第5図はこのデジタル
スイツチの使用の一例を示す正面図、第6図はこ
の考案によるデジタルスイツチの他の例を示す回
路図である。
2a……前面板、4,14……表示器、5,6
……押釦、7,8……メカスイツチ、15……可
逆プリセツトカウンタ、16……表示駆動回路、
17……入出力回路、18……パルス発生回路、
19……入出力制御回路、20……ラツチ回路、
21……リセツト回路、22……駆動選択回路、
35……演算処理回路、101……入力禁止回路
。
FIG. 1 is a side view showing an example of a digital switch according to this invention, FIG. 2 is a circuit diagram showing an example of this digital switch, FIG. 3 is a block diagram showing an example of a drive selection circuit for an operating status indicator, and FIG. Fig. 4 is a block diagram showing an example of an input inhibit circuit in this digital switch circuit, Fig. 5 is a front view showing an example of the use of this digital switch, and Fig. 6 is a circuit showing another example of the digital switch according to this invention. It is a diagram. 2a... Front plate, 4, 14... Display unit, 5, 6
...Push button, 7,8...Mechanical switch, 15...Reversible preset counter, 16...Display drive circuit,
17...Input/output circuit, 18...Pulse generation circuit,
19...Input/output control circuit, 20...Latch circuit,
21...Reset circuit, 22...Drive selection circuit,
35...Arithmetic processing circuit, 101...Input prohibition circuit.
Claims (1)
この可逆プリセツトカウンタのデータ出力および
動作状態を表示する表示器と、この表示器を駆動
する表示駆動回路と、演算処理回路等からの信号
線を入出力および高抵抗の各状態に切り換える入
出力回路と、演算処理回路等からのデータ信号を
可逆プリセツトカウンタに入力させるための制御
信号を上記入出力回路に印加する入出力制御回路
と、前記板側に設定された操作スイツチにより上
記可逆プリセツトカウンタを歩進させるパルス発
生回路とを具備し、上記表示駆動回路は、演算処
理回路等を動作状況と操作スイツチの操作の可否
を動作状態表示器に点灯、消灯もしくは点滅によ
つて選択表示させる駆動選択回路を備えたことを
特徴とするデジタルスイツチ。 (2) 可逆プリセツトカウンタに入力された信号
の一部もしくは全部を保持するラツチ回路を具備
してなる実用新案登録請求の範囲第1項記載のデ
ジタルスイツチ。 (3) 外部の演算処理回路等からの入力禁止信号
が印加されたとき、前面板側に設定された操作ス
イツチから可逆プリセツトカウンタへの入力を禁
止する入力禁止回路を具備してなる実用新案登録
請求の範囲第1項または第2項記載のデジタルス
イツチ。[Claims for Utility Model Registration] (1) A reversible preset counter capable of addition and subtraction;
A display that displays the data output and operating status of this reversible preset counter, a display drive circuit that drives this display, and an input/output that switches the signal line from the arithmetic processing circuit, etc. to each input/output and high resistance state. circuit, an input/output control circuit that applies a control signal to the input/output circuit for inputting a data signal from an arithmetic processing circuit, etc. to the reversible preset counter, and an operation switch set on the board side to control the reversible preset counter. The display drive circuit includes a pulse generation circuit that increments a set counter, and the display drive circuit selectively displays the operation status of the arithmetic processing circuit, etc. and whether or not the operation switch can be operated by lighting, extinguishing, or blinking on the operation status display. A digital switch characterized by being equipped with a drive selection circuit that allows (2) The digital switch according to claim 1, which is provided with a latch circuit that holds part or all of the signal input to the reversible preset counter. (3) A utility model equipped with an input prohibition circuit that prohibits input from an operation switch set on the front panel side to a reversible preset counter when an input prohibition signal from an external arithmetic processing circuit, etc. is applied. A digital switch according to registered claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985104251U JP2588270Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985104251U JP2588270Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6213032U true JPS6213032U (en) | 1987-01-26 |
| JP2588270Y2 JP2588270Y2 (en) | 1999-01-06 |
Family
ID=30977569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985104251U Expired - Lifetime JP2588270Y2 (en) | 1985-07-08 | 1985-07-08 | Digital switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2588270Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6451825A (en) * | 1987-08-24 | 1989-02-28 | Omron Tateisi Electronics Co | Numeral setting device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698671A (en) * | 1979-12-20 | 1981-08-08 | Suisse Horlogerie | Interface unit for inputting data into small device such as watch or clock |
-
1985
- 1985-07-08 JP JP1985104251U patent/JP2588270Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698671A (en) * | 1979-12-20 | 1981-08-08 | Suisse Horlogerie | Interface unit for inputting data into small device such as watch or clock |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6451825A (en) * | 1987-08-24 | 1989-02-28 | Omron Tateisi Electronics Co | Numeral setting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2588270Y2 (en) | 1999-01-06 |
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