JPS6213672B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a character and graphic information display device capable of scrolling display contents when displaying character and graphic information from a digital computer or the like as an image. With the rapid development of LSI technology in recent years, the central processing circuit (hereinafter abbreviated as CPU) of computers
With the emergence of microcomputers that incorporate a single LSI, conventional general-purpose digital IC systems are beginning to shift to CPU-centered systems. In addition to the CPU, such systems also have a playback-only memory circuit (hereinafter referred to as program ROM) that stores CPU processing procedures (programs), and a program ROM that temporarily stores data during CPU processing. The main components are a rewritable memory circuit (hereinafter referred to as data RAM) that can be used in place of a RAM, and an input/output circuit. FIG. 1 is a block diagram showing an example of an image display device using the above-mentioned microcomputer.
In this figure, 1 is a CPU, 2 is a clock generation circuit that generates a clock signal for CPU 1, 3 is a data RAM, 4 is a program ROM, 7 is a character code display circuit that can display character code information, and 8 is a cathode ray tube. This is a typical display device. Also, 13 is
14 is a signal path for transmitting and receiving data between the CPU 1 and each circuit, that is, a data bus;
1 is a signal path for supplying address signals to each circuit, ie, an address bus, and 16 is a clock signal path for supplying a clock signal generated from the clock generation circuit 2. The character code display circuit 7 clocks a display timing pulse generation circuit 71 that generates a synchronization signal of a television signal and an address signal for display, an address bus 14, and a display timing pulse signal path 15 from the display timing pulse generation circuit 71. an address switching circuit 72 that switches in response to a clock signal supplied from the generation circuit 2 via the clock signal path 16; a memory circuit (hereinafter referred to as display RAM) 73 that has a relative positional relationship with the display screen and stores character code information; A reproduction-only memory circuit (hereinafter referred to as character pattern generation ROM) 74 that stores character code patterns corresponding to this character code information in advance, and a parallel signal that converts parallel signals from the character pattern generation ROM 74 into serial signals. It is composed of a serial conversion circuit 75. This character display circuit 7 corresponds to the output circuit of the CPU 1, and in an actual character display device, input circuits such as a keyboard are generally connected via a data bus 13 and an address bus 14, but the present invention It has been omitted because it has no relation to the essence of . FIG. 2 is a diagram showing an example of the address assignment of the system shown in FIG. FIG. 3 is a diagram illustrating timing relationships among signal paths; First, the circuit shown in Figure 1 plays an important role.
The operation of CPU1 will be explained. In FIG. 1, a CPU 1 is a central processing circuit of a so-called microcomputer. The CPU 1 can normally perform arithmetic processing on multiple bits at the same time, but for convenience of explanation, it is assumed here that the CPU is capable of 8-bit parallel arithmetic processing, and the address bus 14 has 16 parallel lines output. In other words, CPU1 is from address 0 to address 2 ¹⁶ - 1 = 65535 (expressed in hexadecimal)
Since the address is FFFF and is easy to represent, it is possible to output address signals up to (hereinafter address representation will be in hexadecimal). Moreover, the data bus 13 is eight parallel lines, and runs from the CPU 1 to each memory circuit (program ROM 4, data RAM 3, display RAM 7).
This is a signal path that sends parallel 8-bit signals to CPU 3) and vice versa. Generally, in a microcomputer system, a CPU 1 and each circuit are connected by the same address bus 14 and the same data bus 13, as shown in FIG. Therefore, in order to separate each circuit, a different address is assigned to each circuit. FIG. 2 shows an example of this address assignment. In Figure 2, program ROM 4 has a total of 4096 addresses from (F000) ₁₆ to (FFFF) ₁₆ .
The address and data RAM 3 are from (0000) ₁₆ to (0FFF) ₁₆ , a total of 4096 addresses, and display RAM 73.
Total from (8000) ₁₆ to (87FF) ₁₆
Address 2048 has been assigned. Microcomputers, like regular electronic computers, store programs, so
The ROM 4 stores processing procedures (programs) for operating the system shown in FIG. Program ROM4 is (F000) ₁₆ as shown in Figure 2.
It occupies 4096 addresses from address to (FFFF) ₁₆ , and the stored contents are read out to the data bus 13 according to the address information on the address bus 14 of the CPU 1.
This memory content is taken in by the CPU 1, decoded as an instruction, and operates this system. That is, a program counter is normally provided inside the CPU 1, and the value indicated by this counter determines the address of the program ROM 4 containing the instruction being executed. Next, this address is output to the address bus 14, and the data stored at that address in the program ROM 4 is taken into the CPU via the data bus 13. CPU1 decodes this data as an instruction,
It operates the entire system by changing the storage contents of the data RAM 3 and the display RAM 73, and by exchanging data with other input/output circuits. FIG. 4 shows the timing relationship among the clock signal, address signal, and data signal during operation. 4a shows the clock signal supplied to CPU 1 by signal path 16, b the address signal passing through signal path 14, and c the data signal passing through signal path 13. FIG. Address signal is CPU1
Since the data signal is output in one direction, the address advances within the _T1 period with a certain time delay from the falling edge of the clock signal, but since the data signal is a bidirectional signal,
The operation is such that output signals are mainly output only during the _T2 period to prevent output signals from competing with each other on the data bus 13. The above is an explanation of the general operation of the CPU 1. Next, the character code display circuit 7 that displays the character code information taken into the CPU 1 on the display 8 will be explained. This circuit is a well-known circuit known as a cycle steal display system.
The feature of this method is that no special processing is required for the CPU 1 to access the display RAM 73, and character codes can be displayed stably.
In other words, as shown in Fig. 4, focusing on the fact that the data signal is sent and received from CRS1 only during the _T2 period of the clock signal, during the _T1 period, the data signal is sent and received from the CRS1 to the CPU1 for display.
This is a method in which the RAM 73 is separated by an address switching circuit 72, a display address signal from the display timing pulse generation circuit 71 is supplied to the display RAM 73 via the address switching circuit 72, and character code information stored therein is read out. . The state of the combined address signal supplied to the display RAM 73 at this time is shown in FIG. 4d. The read character code information is supplied to a character code pattern generation ROM 74 that stores character code patterns in advance, as in other display systems. Furthermore, the display address signal from the display timing pulse generation circuit 71 is also used for character code pattern generation at the same time.
The information is supplied to the ROM 74 and the character code pattern information is read out. The read character code pattern information is supplied to the parallel-to-serial conversion circuit 75 and displayed on the display 8.
It is converted into a signal that can be input to and output. FIG. 3 shows an example of an image displayed on the display 8 in this way.
A total of 1280 character code pattern information can be displayed, 20 in the vertical direction. The character code pattern information displayed here is shown in Figure 2 from display RAM 7, which has a total of 1280 addresses, from (8000) ₁₆ to (84FF) ₁₆ .
It is configured to have a one-to-one correspondence with the character code information stored in the display memory section No. 3. That is, if the location 1,1 in FIG. 3 corresponds to address (8000) ₁₆ , the display timing pulse generation circuit 71 will read out address (8000) ₁₆ at the location 1, 1 in FIG. Display address signal for display
Supply to RAM73. The above is an overview of the character display circuit 7. Next, the displayed character code pattern information is raised in order from the bottom to the top. A so-called vertical scroll display circuit will be explained. FIG. 5 is a block diagram showing a conventional example of an image display device capable of vertically scrolling display. In this conventional example, a data latch circuit 77 and a scroll counter circuit 76 are newly added.
The display address signal output from 1 is converted into a scroll address signal. In FIG. 5, circuits that are the same as those in FIG. 1 are designated by the same reference numerals. Further, FIG. 6 shows an example of address settings during scroll display to explain the operation of FIG. 5. Below, the general operation of FIG. 5 will be described. The data latch circuit 77 is set by the CPU 1 to the first address of the first row of the display screen. For example, as shown in FIG. 6, an address corresponding to the number of scroll lines is set, such as 0 in the initial state where no scrolling is performed, 64 when scrolling up by one line, and 128 when scrolling up by two lines. This set address is preset in the scroll counter circuit 76 before the screen is displayed, and thereafter, according to the display screen, the count of the scroll counter circuit 76 is incremented by one by a signal from the display timing pulse generation circuit 71. Increase by increments. At the same time, the output signal of the scroll counter circuit 76 is supplied to the address switching circuit 72 as a display address signal.
The character code information stored in the display RAM 73 is displayed in the same manner as in the case of FIG. In this case, the new line will be the bottom line, so the contents of the scroll RAM addresses from (8500) ₁₆ to (87FF) ₁₆ shown in Figure 2 will also be displayed on the screen. Further, the scroll counter circuit 76 is
(7FF) It is configured to count up to address ₁₆ (=2 ¹¹ ), and the upper 5 bits of the displayed RAM address are ignored, and the next address after (7FF) ₁₆ is address 0. Therefore, the displayed character code pattern information is from the address specified by the data latch circuit ₇₆ to the _1280th address (horizontal
64, vertically 20) in a relatively one-to-one relationship with the character code information stored. Furthermore, the data set in the data latch circuit 77 shifts by 64 each time one line is scrolled, so the configuration is such that the data cannot be returned to the initial state unless 32 lines are scrolled. With the conventional scroll display described above, it is possible to scroll the entire screen, but it is also possible to scroll only a portion of the display screen, such as scrolling only 15 lines from the top of the screen or 10 lines from the bottom of the screen. There is a drawback that it cannot be done. The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
An object of the present invention is to provide a text/graphic information display device capable of partially scrolling a display screen. In order to achieve the above object, the present invention provides that a display memory address is determined by a count value that advances sequentially from a first value to a second value and returns to the first value when the second value is reached. This display device is provided with specifying means for specifying a count value to start counting, and changing means for changing the specified count value, thereby performing scroll display. Hereinafter, the present invention will be explained in detail with reference to FIGS. 7 to 9. FIG. 7 is a block diagram showing an embodiment of the character/graphic information display device according to the present invention, and the same reference numerals are used for the same circuit parts as in FIGS. 1 and 5. In the figure, 78, 79, 7A, and 7B are data latch circuits, and 78 and 79 are set with numerical values to be preset in the scroll counter circuit 76, similar to the data latch circuit 76 in FIG. Also, 7C, 7
D is a comparison circuit, and 7E is a switching circuit for switching the preset value supplied to the scroll counter circuit 76. Further, FIGS. 8 and 9 are diagrams for explaining the operation of FIG. 7, respectively, and show examples of address settings during scroll display. Now, in FIG. 7, the data latch circuit 7
7, 78, 79, 7A, and 7B can be set freely as in the case of Fig. 5, but here, for convenience of explanation, the following values are set in each latch circuit by CPU1. shall be set accordingly. The data latch circuit 77 has the first address to be displayed on the first line of the display screen as in the case of FIG. 5, the data latch circuit 78 has the first address of the display memory, and the data latch circuit 79 has the first address to be displayed on the third line of the display screen. The first address to be displayed, the data latch circuit 7A, is the first address on the third line of the display screen, the data latch circuit 7A.
The address next to the final address of the display memory is set in B, respectively. First, consider the case where the entire screen is scrolled as shown in FIG. In this case, the data latch circuits 79, 7 in FIG.
A and the comparison circuit 7C are unnecessary. That is,
As in the case of FIG. 5, the scroll counter circuit 7
6, the numerical value of the data latch circuit 77 is preset via the switching circuit 7E before the screen is displayed, and thereafter, counting is performed sequentially from this numerical value according to the displayed screen. Scroll counter circuit 76
The output signal of is supplied to the address switching circuit 72 as in the case of FIG.
Also supplied. Since the output of the data latch circuit 7B is supplied to the other input of the comparison circuit 7D, the scroll counter circuit 76 performs counting, and the address next to the last address of the display memory,
That is, when the process advances to address (8500) ₁₆ in FIG. 2, a change occurs in the output signal of the comparator circuit 7D. The output of the comparator circuit 7D is supplied to the switching circuit 7E, and at the point when a change occurs, the switching circuit 7E switches the scroll counter circuit 76 so that the data latch circuit 78 is connected instead of the data latch circuit 77, and at the same time connects the scroll counter circuit 76 to the data latch circuit 78 instead of the data latch circuit 77. The value of the data latch circuit 78 is preset in the circuit 76. Therefore, in Figure 6, the display screen
Address 1280 [equivalent to address (8500) ₁₆ ] and above is converted to address 0 [equivalent to address (8000) ₁₆ ] as shown in Figure 8, and a ring is just created using one screen's worth of memory. , the structure is such that it is displayed in a shifted manner,
The memory capacity required for display is 64× in the case of Figure 3.
20=1280 bytes, which is 768 bytes less than the configuration shown in FIG. 5 due to the capacity of the scroll memory. If you scroll another 20 lines, the screen position will match the initial state, so the data value set in the data latch circuit 77 can be just the value of the number of lines to be scrolled, and there is almost no need to calculate the data value. . This is because the numbers preset to the scroll counter circuit 76 are address 0, address N, and N, where N is the number of addresses displayed in one horizontal line.
Since this is address 2N and the first address of each line, if each address is represented in binary, one line corresponds to address 64 in this case, so the first address of each line will be as shown in the table below.

[Table] Therefore, in this case, the lower 6 bits of the binary representation are always 0, so the value set in the latch circuit 77 may be a value corresponding to the upper 5 bits,
Moreover, the value is exactly the same as the number of scroll lines, so there is no need to calculate the setting data value. In addition, in the above example, we explained that the display RAM addresses from (8000) ₁₆ to (84FF) ₁₆ are displayed, but by using a different address, from (8300) ₁₆ to (87FF) ₁₆ If we consider the case of displaying up to 1, the data set in the data latch circuit 77 will be a value that is shifted by (300) ₁₆ addresses [= 768 addresses] from the case of Fig. 8, and some calculation of the set data value will be required. becomes. However, in this case, when the value of the data latch circuit 78 is preset to the scroll counter circuit 76, the value of the scroll counter circuit 76 becomes the next one after (7FF) ₁₆ , and only the upper one bit is observed. There is also the advantage that the data latch circuit 7B and the comparator circuit 7D are not required because the data can be easily determined. Next, consider a case where a portion of the screen is scrolled as shown in FIG. In this case, the comparison circuit 7C compares the output of the display timing pulse generation circuit 71 and the output of the data latch circuit 7A,
If they match, the switching circuit 7E switches the data latch circuit 79 to be connected to the scroll counter circuit 76, and presets the scroll counter circuit 76 at the same time. In the example shown in FIG. 9, the first address of the third row, 128, is set in the data latch circuit 7A, and the data latch circuit 79 controls scrolling. In the case of FIG. 9, an example is shown in which the third and subsequent lines are scrolled, but of course it is also possible to set data such that the third and subsequent lines are scrolled and the third and subsequent lines are fixed.
In that case, it is easy to imagine that the data latch circuit 77 will control the scrolling. Moreover, not only the third line but also any line can be used as the first line or the last line of partial scrolling, which can be easily realized by changing the set value of the data latch circuit 79. In addition, data latch circuits 79 to 7B in FIG.
It is clear from the examples in FIGS. 8 and 9 that it is not necessary to be able to set all of the values from the CPU 1. Therefore, for fixed numerical values, a simple data setting circuit is sufficient. The several examples mentioned above have all been explained using character display devices, but there is no ROM 74 for character pattern generation, the display RAM 73 and parallel-to-serial conversion circuit 75 are directly connected, and the contents of the display RAM are displayed as they are. The present invention can also be applied to pattern display devices. As described above, according to the present invention, scrolling display can be performed on only a portion of the display screen. In addition, the capacity of display RAM of 2 ⁿ addresses, which was conventionally required, can be made equal to the number of character code patterns to be displayed, for example.
In the case of a 64 x 20 pattern, the RAM capacity that conventionally required 2048 bytes is reduced to 1280 bytes, making it possible to construct display circuits at low cost. Furthermore, since the number of lines to be scrolled matches the number of lines that can be displayed on the screen, the capacity of the program to process scrolling is reduced, which also makes it cheaper. Furthermore, since the program capacity is reduced, the processing time required for the program can be shortened, and there is an advantage that high-speed scrolling operation is also possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional text and graphic information display device, FIG. 2 is an address allocation diagram showing an example of the address assignment of the text and graphic information display device shown in FIG. 1, and FIG.
4 is a timing chart showing the timing relationship of the main signals of the text and graphics information display device shown in FIG. 1. FIG. 5 is a conventional text and graphics information display capable of scrolling display. A block diagram showing the device, FIG. 6 is an address status diagram showing the correspondence between the display image position and memory address during scroll display, and FIG. 7 is a block diagram showing an embodiment of the text and graphic information display device according to the present invention. ,
Figure 8 is an address status diagram showing the correspondence between the display image position and memory address during full-screen scroll display, and Figure 9 is an address status diagram showing the correspondence between the display image position and memory address during partial scroll display. It is a diagram. 1: Central processing circuit, 7: Character code display circuit, 71: Display timing pulse generation circuit, 7
3: Display RAM, 77, 78, 79, 7A, 7
B: data latch circuit, 7C, 7D: comparison circuit,
7E: Switching circuit.

Claims (1)

[Claims] 1. A memory means for storing character and graphic information, a counting means for sequentially changing the count value at a predetermined period, and a memory means for reading out and displaying the character and graphic information stored in the memory means using the count value of the counting means as a memory address. A display device comprising a reading display means is provided with a designation means for designating a plurality of count initial values at which the counting means starts counting, and a setting means for setting the designated count initial value at each predetermined period. Characteristic character and graphic information display device.