JPS6214751U - - Google Patents

Info

Publication number
JPS6214751U
JPS6214751U JP1985104113U JP10411385U JPS6214751U JP S6214751 U JPS6214751 U JP S6214751U JP 1985104113 U JP1985104113 U JP 1985104113U JP 10411385 U JP10411385 U JP 10411385U JP S6214751 U JPS6214751 U JP S6214751U
Authority
JP
Japan
Prior art keywords
chips
pad
substrate
inorganic
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985104113U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985104113U priority Critical patent/JPS6214751U/ja
Publication of JPS6214751U publication Critical patent/JPS6214751U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例の断面図、第２図は
従来例の断面図、第３図は本考案の製法を示す斜
視図、第４図Ａ，Ｂは本考案の一実施例の断面図
、第５図は本考案の一実施例の断面図である。 ３……基板、４……ハンダ球、５……チツプ、
１０……配線、１１……ＥＣパツド。 Fig. 1 is a cross-sectional view of an embodiment of the present invention, Fig. 2 is a cross-sectional view of a conventional example, Fig. 3 is a perspective view showing the manufacturing method of the present invention, and Fig. 4 A and B are an embodiment of the present invention. FIG. 5 is a cross-sectional view of one embodiment of the present invention. 3... Board, 4... Solder ball, 5... Chip,
10...Wiring, 11...EC pad.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の集積回路チツプが搭載され、これらチツ
プの機能検査あるいは技術変更を行うＥＣパツド
を有する無機あるいは有機基板において、該チツ
プと該基板とを電気的に接続する配線リードまた
はハンダ球が設けられた面と異なる角度あるいは
レベルの面上にＥＣパツドを設けたことを特徴と
するマルチチツプモジユール。 An inorganic or organic substrate on which a plurality of integrated circuit chips are mounted and has an EC pad for functional testing or technology modification of these chips, and is provided with wiring leads or solder balls for electrically connecting the chips to the substrate. A multi-chip module characterized by having an EC pad provided on a surface at a different angle or level from the surface.
JP1985104113U 1985-07-10 1985-07-10 Pending JPS6214751U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985104113U JPS6214751U (en) 1985-07-10 1985-07-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985104113U JPS6214751U (en) 1985-07-10 1985-07-10

Publications (1)

Publication Number Publication Date
JPS6214751U true JPS6214751U (en) 1987-01-29

Family

ID=30977304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985104113U Pending JPS6214751U (en) 1985-07-10 1985-07-10

Country Status (1)

Country Link
JP (1) JPS6214751U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766359A (en) * 1993-08-31 1995-03-10 Nec Corp Multi-chip module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766359A (en) * 1993-08-31 1995-03-10 Nec Corp Multi-chip module

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